FEE Electronics progress Mezzanine layout progress FEE64 progress FEE64 initial testing Test mezzanine. A few of the remaining tasks 2nd October 2009.

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FEE Electronics progress Mezzanine layout progress FEE64 progress FEE64 initial testing Test mezzanine. A few of the remaining tasks 2nd October 2009

Mezzanine Layout Progress 2nd October 2009 Layout changed after last meeting. Changes made after discussions with ST and DB.- Approved. PCB manufacturer requested changes in progress. Cost of 30 pcbs :£3,626 Cost of assembly:£3,400 Delivery 6 weeks.

FEE64 progress and targets September 30 th : –First board completed power supply checks and Virtex5 recognised using JTAG. –Design and assembly faults rectified. October 2 nd : –Remaining boards submitted to Electronics Workshop for modification. –Virtex5 commissioning commences - MK, LM. October 31 st : –Milestone --- Decision to proceed with experiment. 2nd October 2009

Initial testing of FEE64 Power supplies – 28 : Check for noise, stability, accuracy, efficiency…. FPGA – –Check configuration via JTAG. –Check processor operates with internal memory and terminal. –Check configuration from EEPROM. DDR2 Memory –Run test system developed by DSDG. –Check results and optimise access speed for best performance. Gbit Ethernet –Run test system developed by DSDG. ASIC communications and discriminator output timing Analog buffers and ADCs 2nd October 2009

Test mezzanine The board is to allow the exercising of the FEE64 analog and digital inputs. Target is to produce them by Mid October. Cost of manufacture for 2 assembled and 8 spare pcbs is £1, – Can I go ahead ? 2nd October 2009

A few of the remaining Tasks Manufacture Mezzanine. Complete Mechanical design. ( Is waiting for final component heights ) Test documentation. Commission first FEE64 units VHDL for first experimental use. –Full Linux processor with peripherals and DMA ( from DSDG work ) –ASIC communications ( from prototype work ) –ASIC multiplexed readout. ( from prototype work ) Timestamped based on discriminator signals. Formatted and transferred to processor memory as four time ordered data streams. FEE64 design documentation. Prepare for production. 2nd October 2009