CSET 4650 Field Programmable Logic Devices Introduction to PLAs Programmable Logic Arrays CSET 4650 Field Programmable Logic Devices For additional information, contact any of the following individuals: Dan Solarek Professor and Chairman dsolarek@utnet.utoledo.edu dsolarek@eng.utoledo.edu Voice: 419-530-3377 Allen Rioux Director of Online Services arioux@toledolink.com arioux@utnet.utoledo.edu To leave a message for any of these individuals call the department secretary at 419-530-3159. You may send a FAX to 419-530-3068 Dan Solarek Richard Springman Director of Student Services rspringm@utnet.utoledo.edu rspringm@eng.utoledo.edu Voice: 419-530-3276 Myrna Swanberg Academic Program Coordinator mswanbe@utnet.utoledo.edu mswanber@eng.utoledo.edu Voice: 419-530-3062

Programmable Logic Array (PLA) Introduced in 1975 Predates the invention of the PAL The first PLD The most user-configurable of the traditional two-level programmable logic devices

Programmable Logic Array (PLA) A PLA is a large 2-level AND / OR array with lots of inputs and product terms Most general/flexible device of this architecture PROM, PAL, PLA Programmable connections for both AND / OR Uses the sum of products (SOP) form

PLA Block Diagram Same 2-level AND/OR logic arrangement as with PROM and PAL devices programmable shareable

PLA Description the third simple PLD we will study decode only some of the input addresses (PROMs decoded all of them) increased propagation delay because of both the AND and OR array inputs are programmable naming convention not as systematic as PALs also called FPLAs

PLA: A More General Idea A PAL has limits on the arrangement of its sum-of-products groupings. Programmed Array Logic A PLA has complete flexibility of its sum-of-products groupings. Programmable Logic Array

Programmable Logic Array (PLA) n input variables AND gates have 2n inputs true and inverted form of each input variable m outputs driven by large OR gates each AND gate is programmably connected to each output’s OR gate (shareable product terms)

Nomenclature: 4x6x3 PLA

Compact Representation Illustration of a 4-input, 6 product term, 3-output PLA 4x6x3 All fuses shown intact (not yet programmed) This representation is closer to the “wired logic” physical implementation

PLA Electrical Design fuse detail Wired Logic fuse detail

PLA: Sharing Product Terms B A C D F G H J ABC ABC AD F = ABC + AD + AD G = ABC + ABC + AD H = ABC + BD J = B + AD AD BD B

Sharing Product Terms P1 P2 P3 P4 P5 P6

Example: Programming a PLA Given: F1 = Σm(2, 4, 5, 7) F2 = Σm(0, 1, 2, 4, 6) Use K-maps to minimize and look for common product terms Program functions into a simple PLA minterm form

F1 K-Map Minimization B BC ABC A C AC AB Three-variable K-map for F1 = Σm(2, 4, 5, 7) C B A 1 3 2 4 5 7 6 BC ABC F1 AB AC

F2 K-Map Minimization B BC BC A C AC Three-variable K-map for F2 = Σm(0, 1, 2, 4, 6) C B A 1 3 2 4 5 7 6 BC BC F2 AC

Programming the PLA Product Terms AB AC BC ABC

XOR: Like a programmable inverter … Programming XOR: Like a programmable inverter … Tied to 0 – F1 not inverted Tied to 1 – F1 is inverted

PLA Example 2 Functions to implement are: = ABC + ABC + ABC + ABC standard form

Group both 1s and 0s to find fewest product terms Minimum Product Terms Fewest are Group both 1s and 0s to find fewest product terms

PLA Programming Table Indicates intact fuse locations true or complemented Indicates intact fuse locations Helps to identify shared terms

PLA For Example 2 3 inputs 4 product terms 2 outputs optional inversion of outputs

Circuit For Example 2 Note the inversion of the output to generate F1

Before Programming Express functions in SOP form Try to reduce the number of product terms To use fewer of the rows Look at both 1s and 0s Number of literals in each term not as important Fewer may make circuit faster

Create Programming Table What really gets generated is the programming table Chip programmed in special-purpose programming device uses personality modules for different devices

PROM, PAL, PLA Assignment Sandige, Chapter 7 7 – 39 7 – 42 7 – 44 7 – 48 Write out on paper & photocopies from book Due on Wednesday, September 8, 2004 at start of class