Altera Technical Solutions Seminar 2000

Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration Intellectual Property Design Iteration Design Optimization Internet Interface Roadmap Quartus Demo

Agenda Introduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration Intellectual Property Design Iteration Design Optimization Internet Interface Roadmap u Routing Structure u CoreSyn™ Synthesis u Floorplanning

Relative Delay Potential Delay Gap

MegaLAB Level Eliminates Gap Relative Delay

MegaLAB Helps Optimize Speed EmbeddedSystemBlock(ESB) LAB16LAB1LAB2 LE MegaLAB Interconnect 160 LEs of Logic, Plus 2K RAM or 16 Macrocells

MultiCore Performance Benefits 161 MHz 166 MHz 16-State, 5-Input/ Output State Machine 129 MHz 161 MHz FLEX 10KE APEX 20K Function MAX 7000AE 5 x 5 Registered I/O Multiplier 166 MHz 59 MHz

Embedded Product-Term Performance 8.6 ns4.8 ns t SU 2.9 ns P-TERM EPF10K100E-1EPM7064S-5 t CO 4.7 ns t D 1.0 ns REGLUTREG t SU 0.7 ns t LAD 3.9 ns REG P-TERM APEX 20K-1 Speed Grade t CO 0.2 ns REGLUT

CoreSyn ™ Synthesis Optimizes Mapping LUT P-Term Memory CoreSyn Synthesis PLL WriteMemoryControl ReadMemoryControl MemoryController Usage Parameter Control S/M FIFO Can Be Performed Manually or Automatically

Efficient Floorplan Editor  Flexible Editing Capabilities Multi-Level Undo/Redo Multi-Level Undo/Redo Drag-and-Drop Assignments into Other Quartus Windows Drag-and-Drop Assignments into Other Quartus Windows Grouped Drag-and-Drop Grouped Drag-and-Drop  All Nodes Can Be Automatically Located in Source File

Optimization Summary  Optimize for Density and/or Performance  MegaLAB Provides Higher Performance  CoreSyn Synthesis for Optimal Implementation  Floorplanner Allows Quick Identification of Paths and Delays