Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 1 Read-out of High Speed S-LINK Data Via a Buffered PCI Card A. Guirao.

Slides:



Advertisements
Similar presentations
Nios Multi Processor Ethernet Embedded Platform Final Presentation
Advertisements

1 iTOP Electronics Effort LYNN WOOD PACIFIC NORTHWEST NATIONAL LABORATORY JULY 17, 2013.
Who We Are? Detector Building Group of KFKI-RMKI (Research Institute for Particle and Nuclear Physics), Budapest, HUNGARY.
CMS Week Sept 2002 HCAL Data Concentrator Status Report for RUWG and Calibration WG Eric Hazen, Jim Rohlf, Shouxiang Wu Boston University.
Super Fast Camera System Performed by: Tokman Niv Levenbroun Guy Supervised by: Leonid Boudniak.
An ATCA and FPGA-Based Data Processing Unit for PANDA Experiment H.XU, Z.-A. LIU,Q.WANG, D.JIN, Inst. High Energy Physics, Beijing, W. Kühn, J. Lang, S.
28 August 2002Paul Dauncey1 Readout electronics for the CALICE ECAL and tile HCAL Paul Dauncey Imperial College, University of London, UK For the CALICE-UK.
DAQ WS02 Feb 2006Jean-Sébastien GraulichSlide 1 Does IPM System Matches MICE needs ? Personal Understanding and Remarks o General Considerations o Front.
Takeo Higuchi Institute of Particle and Nuclear Studies, KEK; On behalf of COPPER working group Jan.20, 2004 Hawaii, USA Super B Factory Workshop Readout.
A presentation by Angela Little SULI Program 8/4/04 Pulsar Boards and the Level II Trigger Upgrade at CDF.
PCIe based readout U. Marconi, INFN Bologna CERN, May 2013.
Module I Overview of Computer Architecture and Organization.
CALICE – 12/07/07 – Rémi CORNAT (LPC) 1 ASU and standalone test setup for ECAL MAIA BEE project Overview DAQ dedicated Sensor test In situ debug and maintenance.
Xilinx at Work in Hot New Technologies ® Spartan-II 64- and 32-bit PCI Solutions Below ASSP Prices January
5 Feb 2002Alternative Ideas for the CALICE Backend System 1 Alternative Ideas for the CALICE Back-End System Matthew Warren and Gordon Crone University.
Ross Brennan On the Introduction of Reconfigurable Hardware into Computer Architecture Education Ross Brennan
DDL hardware, DATE training1 Detector Data Link (DDL) DDL hardware Csaba SOOS.
Using PVSS for the control of the LHCb TELL1 detector emulator (OPG) P. Petrova, M. Laverne, M. Muecke, G. Haefeli, J. Christiansen CERN European Organization.
SLAAC SV2 Briefing SLAAC Retreat, May 2001 Heber, UT Brian Schott USC Information Sciences Institute.
RiceNIC: A Reconfigurable and Programmable Gigabit Network Interface Card Jeff Shafer, Dr. Scott Rixner Rice Computer Architecture:
LECC2003 AmsterdamMatthias Müller A RobIn Prototype for a PCI-Bus based Atlas Readout-System B. Gorini, M. Joos, J. Petersen (CERN, Geneva) A. Kugel, R.
14 Sep 2005DAQ - Paul Dauncey1 Tech Board: DAQ/Online Status Paul Dauncey Imperial College London.
Markus Joos, EP-ESS 1 “DAQ” at the El. Pool Aim and preconditions Hardware Operating system support Low level software Middle level software High level.
U N C L A S S I F I E D FVTX Detector Readout Concept S. Butsyk For LANL P-25 group.
Understanding Data Acquisition System for N- XYTER.
Design and Performance of a PCI Interface with four 2 Gbit/s Serial Optical Links Stefan Haas, Markus Joos CERN Wieslaw Iwanski Henryk Niewodnicznski Institute.
Bart Hommels Univeristy of Cambridge EUDET Annual Meeting, Ecole Polytechnique, Paris JRA3: DAQ Overview Objectives System Overview Status of.
B. Hirosky 10/17/00 ‘L2ßeta’ CPU Concept Commercial 6U CPU Card W/ UII on board FPGA MBUS P I/O + DMA ECL Latch Driver MBUS Straight pass to VME Latches.
R&D for First Level Farm Hardware Processors Joachim Gläß Computer Engineering, University of Mannheim Contents –Overview of Processing Architecture –Requirements.
David Abbott - JLAB DAQ group Embedded-Linux Readout Controllers (Hardware Evaluation)
A PCI Card for Readout in High Energy Physics Experiments Michele Floris 1,2, Gianluca Usai 1,2, Davide Marras 2, André David IEEE Nuclear Science.
Network Architecture for the LHCb DAQ Upgrade Guoming Liu CERN, Switzerland Upgrade DAQ Miniworkshop May 27, 2013.
Gueorgui ANTCHEVPrague 3-7 September The TOTEM Front End Driver, its Components and Applications in the TOTEM Experiment G. Antchev a, b, P. Aspell.
EUDRB: the data reduction board of the EUDET pixel telescope Lorenzo Chiarelli, Angelo Cotta Ramusino, Livio Piemontese, Davide Spazian Università & INFN.
Frank Lemke DPG Frühjahrstagung 2010 Time synchronization and measurements of a hierarchical DAQ network DPG Conference Bonn 2010 Session: HK 70.3 University.
Next Generation Operating Systems Zeljko Susnjar, Cisco CTG June 2015.
Design Criteria and Proposal for a CBM Trigger/DAQ Hardware Prototype Joachim Gläß Computer Engineering, University of Mannheim Contents –Requirements.
David Abbott - Jefferson Lab DAQ group Data Acquisition Development at JLAB.
Serial Data Link on Advanced TCA Back Plane M. Nomachi and S. Ajimura Osaka University, Japan CAMAC – FASTBUS – VME / Compact PCI What ’ s next?
Latest ideas in DAQ development for LHC B. Gorini - CERN 1.
Guido Haefeli CHIPP Workshop on Detector R&D Geneva, June 2008 R&D at LPHE/EPFL: SiPM and DAQ electronics.
Sep. 17, 2002BESIII Review Meeting BESIII DAQ System BESIII Review Meeting IHEP · Beijing · China Sep , 2002.
Connecting EPICS with Easily Reconfigurable I/O Hardware EPICS Collaboration Meeting Fall 2011.
DEPARTEMENT DE PHYSIQUE NUCLEAIRE ET CORPUSCULAIRE JRA1 - Data Acquisition Status Report Daniel Haas DPNC Genève Extended SC Meeting 1 Sep 2008.
Links from experiments to DAQ systems Jorgen Christiansen PH-ESE 1.
Bob Hirosky L2  eta Review 26-APR-01 L2  eta Introduction L2  etas – a stable source of processing power for DØ Level2 Goals: Commercial (replaceable)
Gueorgui ANTCHEV PH-TOT TOTEM Collaboration Meeting – March TOTEM System in H8 - Overview, Block Diagram and Main Characteristics Applications -
Ken Wyllie, CERN Tracker ASIC, 5th July Overview of LHCb Upgrade Electronics Thanks for the invitation to Krakow!
DAQ Overview + selected Topics Beat Jost Cern EP.
CPT week May 2003Dominique Gigi CMS DAQ 1.Block diagram 2.Form Factor 3.Mezzanine card (transmitter SLINK64) 4.Test environment 5.Test done 1.Acquisition.
B. Hirosky 12/14/00 FPGA + FIFO replaces: DMA P/IO buffers TSI device Keep ECL drivers BUY THIS! Same Basic Concept as L2Alpha, but with simplified implementation.
Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Presented by S. Quinton.
KM3NeT Offshore Readout System On Chip A highly integrated system using FPGA COTS S. Anvar, H. Le Provost, F. Louis, B.Vallage – CEA Saclay IRFU – Amsterdam/NIKHEF,
COMPASS DAQ Upgrade I.Konorov, A.Mann, S.Paul TU Munich M.Finger, V.Jary, T.Liska Technical University Prague April PANDA DAQ/FEE WS Игорь.
DAQ Selection Discussion DAQ Subgroup Phone Conference Christopher Crawford
Super BigBite DAQ & Trigger Jens-Ole Hansen Hall A Collaboration Meeting 16 December 2009.
The Evaluation Tool for the LHCb Event Builder Network Upgrade Guoming Liu, Niko Neufeld CERN, Switzerland 18 th Real-Time Conference June 13, 2012.
CHEP 2010, October 2010, Taipei, Taiwan 1 18 th International Conference on Computing in High Energy and Nuclear Physics This research project has.
The ALICE Data-Acquisition Read-out Receiver Card C. Soós et al. (for the ALICE collaboration) LECC September 2004, Boston.
E. Hazen -- HCAL Upgrade Workshop1 MicroTCA Common Platform For CMS Working Group E. Hazen - Boston University for the CMS Collaboration.
PANDA collaboration meeting FEE session
Enrico Gamberini, Giovanna Lehmann Miotto, Roland Sipos
Dominique Gigi CMSweek 6 June 2003
Group Manager – PXI™/VXI Software
Read-out of High Speed S-LINK Data Via a Buffered PCI Card
8-layer PC Board, 2 Ball-Grid Array FPGA’s, 718 Components/Board
Bus-Based Computer Systems
Network Processors for a 1 MHz Trigger-DAQ System
DCM II DCM II system Status Chain test Schedule.
SVT detector electronics
Presentation transcript:

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 1 Read-out of High Speed S-LINK Data Via a Buffered PCI Card A. Guirao Talk for the 4 th PCaPAC International Workshop CERN- EP division, ED Electronics group A.Guirao, F. Bal, M.E. Castro, H.Müller, K. Wyllie, CERN S.Jolly, Imperial College London F.Ballester, UPV

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 2 Contents Introduction to project requirements Minimizing a previous test system What the PC architecture and PCI offer The concept of the new solution Building the real system S-LINK Front-end electronics PCI hardware readout controller Software control interface Performance Conclusions and outlook

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 3 Project Requirements Laboratory test system for LHCb RICH Pixel Chips Test system on-line within 3 months 40MHz clock rate 1MHz event-rate, 32 DWORDs burst per event Inexpensive Flexible functionality Portable and handy– different applications Chip characterisation Wafer testing Module (Photodetector) testing Testbeams

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 4 READOUT CTRLER (CPU) READOUT CARD I/O Minimizing a PIXEL chip test system Solution for the previous version of the pixel chip (10MHz test system) READOUT CARD I/O BACKPLANE BUS CRATE DETECTOR (PIXEL CHIP) DAQ computer New solution PCI BUS CTLER I/O CTLER I/O DAQ computer

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 5 The PC architecture and PCI Advantages: CPUs and many hardware resources available Most common and familiar bus architecture FPGA support Any conventional OS works with the PCI Low cost Partitionable (several controllers per bus) PCI cPCI available Drawbacks:  Limited space for electronics  Limited power

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 6 Concept of the new solution PCI READOUT CONTROLLER FPGA I/Os Custom protocol APPLICATION LAYER HAL SYSTEM HARDWARE HOST BRIDGE ON-BOARD MEMORY SYSTEM MEMORY CPU DLL/module HARDWARESOFTWARE

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 7 Building a real system 1 2

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 8 S-LINK Front-End electronics Single mode (32 dwords for LHCb) or multievent readout mode (up to 16 events per trigger) Adaptation of S-LINK bus width for LVDS serializers

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 9 PCI Readout Controller The FLIC card Standard PCI card  small, familiar Easy to use (Plug&Play) General Purpose solution Mezzanine cards interchangeable Custom HW interface (FPGA, HDL) Low cost Large data buffer  local memory becomes system memory FPGA LOGIC

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 10 Readout Software LabView Analysis and Interface Existing analysis software for the chip Interface with commercial cards (JTAG controller) Need of developing a Windows TM driver for the FLIC Existing support for Linux

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 11 Performance DATA SOURCE LHCb pixel mode 40MHz clock 32 dwords burst SLINK SLINK FLIC 132MB/s payload FLIC input 132MB/s SDRAM 64MB MEMORY BANKS HARDWARE SOFTWARE PCI LabView interface 3MB/s REAL-TIME OFFLINE Jungo driver FLIC specific DLL

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 12 Conclusions and Future Conclusions A test system has been built based on PCI controller 40MHz performance reached More systems have been reproduced in short time Low cost per system Works under LabView Logically compatible with the previous test system Easy maintenance and upgrading Future possibilities Scalability: several readout controllers per PC Higher speed in the software domain (DMA engines) More complex controllers may fit in larger FPGAs

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 13 Thanks!