ECE 448: Spring 2013 Lab 5 FPGA Design Flow Based on Aldec Active-HDL Fast Reflex Game

Part 1: Distribution of FPGA boards Part 2: Diagnostics of FPGA boards Part 3: Introduction to FPGA Design Flow based on Aldec Active-HDL Part 4: Introduction to Lab 5 Part 5: Demos of Lab 4 & late demos of Lab 3 Agenda for today

Parts 1 & 2 Distribution and Diagnostics of FPGA Boards

Part 3 Hands-on Session on FPGA Design Flow based on Aldec Active-HDL

Part 4 Introduction to Lab 5

Task 1 Experimental Testing of Lab 4 for Task 5 & Lab 4 for Task 6

LAB4 for TASK5

rst clk en CNTR UP rst clk en MISR ld rst clk en LFSR X”00” IVBloadB rst OR loadB nexti 1 0 cnz ld rst clk en LFSR X”00” IVAloadA rst OR loadA 1 0 cnz clk LAB2 AB XY sel En ‘0’‘0’ 8 clk rst 8 YSGN nexti nexto rst clk en MISR 8 clk rst 8 XSGN nexto 10 k k k ≠ 0 cnz = X”3FF” 10 done rst clk nexto OR AND not done nexto step run AND cnz LAB3e XoutAout A 8 8 B 8 8 Yout 8 Boutkout 10 k

BTNL BTNS Debouncer RED loadA Debouncer RED run D Q ‘1’‘1’ en rst clk rst clk BTNR Debouncer RED loadB rst clk rst clk rst clk rst clk BUTTON_UNIT BTNU Debouncer RED step rst clk rst clk BTND Debouncer RED next_out rst clk rst clk rst

Debouncer rst clk

Generics of the Debouncer k – size of the counter DD – debouncing period in clock cycles Please make sure that: DD  T CLK ≈ 10 ms 2 k > DD

Rising Edge Detector - RED input clk output rst

SWIVA SWITCH_UNIT IVB 8 8 8

Counter UP COUNTER UP Counter UP q(k-1..k-2) AN Counter UP SEG(6..0) Cou nter UP rst clk OC SSD_DRIVER OC – One’s Complement

Multiplexing Digits

Generics of the SSD_DRIVER 1 ms ≤ Refresh period ≤ 16 ms 1 ms ≤ 2 k  T CLK ≤ 16 ms f CLK = 100 MHz k = ? k – size of the internal counter. Refresh period = 2 k clock cycles.

CLOCK BTNL CLK_RST_1 BTNR rst clk

LAB4 for TASK6

CLK_RST_2 DCM_SP IBUFG BUFG CLOCK locked clk_ibufg clk100 rst clkin clkfb clk0 rst BTNL BTNR rst_or clkfx clk BUFG clkfx_obufg clk0_obufg ‘0’‘0’ 0 1 BUFGMUX

Task 2 Verifying Maximum Experimental Clock Frequency

CLK_RST_3 IBUFG BUFG CLOCK locked clk_ibufg clk100 rst clkin clkfb clk0 rst BTNL BTNR rst_or clkfx clk BUFG clkfx_obufg clk0_obufg 0 1 BUFGMUX SW(0) ODDR2 D0 D1 C0 C1 CE R S Q CLOCKFX ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ clkfxclkfx_180 ODDR2 D0 D1 C0 C1 CE R S Q CLOCK100 ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ clk100clk100_180 clk180 clkfx180 BUFG clk100_180 clk180_obufg BUFG clkfx_180 clkfx180_obufg

LAB5 for TASK2 BTNLBTNRBTNUBTNDBTNS loadAloadBsteprun BTNLBTNRBTNUBTNDBTNS loadAloadBsteprun BUTTON_UNIT SWITCH_UNIT SW IVAIVB LAB3e SEG AN SEGAN hex0 hex1 hex2 hex3 hex0 hex1 hex2 hex3 SSD_DRIVER XSGNYSGNXoutYoutAoutBoutk XSGNYSGNXYABk next_out LED TASK5 CLOCK CLK_RST_3 BTNR clk rst clk rst clk rst clk rst clk rst SW(0) CLOCKFX CLOCK100 BTNL

Verifying Maximum Clock Frequency The circuit should work correctly for SW(0) = 1 => clk = clk100 => f CLK = 100 MHz The circuit should fail for SW(0) = 0 => clk = clkfx => f CLK > maximum f CLK

DCM_SP_inst : DCM_SP generic map ( CLKDV_DIVIDE => 2.0, -- CLKDV divide value -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16). -- Divide value on CLKFX outputs - D - (1-32) -- Multiply value on CLKFX outputs - M - (2-32) -- CLKIN divide by two (TRUE/FALSE) -- Input clock period specified in nS -- Output phase shift (NONE, FIXED, VARIABLE) -- Feedback source (NONE, 1X, 2X) CLKFX_DIVIDE => …………., CLKFX_MULTIPLY => ………, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 10.0, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "1X”, Setting frequency of clkFX during DCM_SP Instantiation

Observing CLOCK100 and CLOCKFX using Oscilloscope Using oscilloscope and two versions of your implementation (with different values of generics of DCM_SP) show the clock signal for the following three cases: A.f CLK = 100 MHz B.f CLK = maximum clock frequency returned by the tools C.f CLK = 10 MHz Document your findings using digital photos. Discuss your observations.

NET "CLOCK100" LOC = "…….." | IOSTANDARD = "LVCMOS33"; NET "CLOCKFX" LOC = "…….." | IOSTANDARD = "LVCMOS33”; New Lines in the User Constraint File (UCF) Select two arbitrary board pins that would be the most easy to observe, and have a relatively large physical distance from each other (to avoid interference).

Task 3 Fast Reflex Game

Rules of the Game (1) BCD Counter is initialized with seconds. After pressing start_stop the counter starts counting down every 0.01 second: 9.99, 9.98, 9.97, …, 0.02, 0.01, 0.00, -0.01, … The goal is to press the start_stop button again as close as possible to After the second press, the counter is stopped.

Rules of the Game (2) The last obtained result can be a. stored with the press of the store button b. skipped with the press of the skip button. After performing these operations the counter is again initialized to Only the last 4 stored results are remembered by the system. The minimum and the maximum absolute value of these last 4 stored results is calculated. The clear button clears the storage, and initializes the counter to

Meaning of Buttons clearstart_stop next_out store skip BTNLBTNR BTNU BTND BTNS

Rules of the Game (3) The next_out button allows displaying 1. current value of the counter 2. the last stored result 3. the result with the minimum absolute value 4. the result with the maximum absolute value. After each press of the next_out button, the mode of display changes to the next one in the wrap-around fashion. The current mode is also indicated with an appropriate number of the rightmost LEDs turned on (1 for the current value of the counter, 2 for the last stored result, etc.)

CD_mod_9 b(3) X”1”X”1” 4 4 b(4) en bout init ld rst clk D(3) CD_mod_9 X”0”X”0” 4 4 en bout init ld rst clk D(2) CD_mod_9 X”0”X”0” 4 4 en bout init ld rst clk D(1) CD_mod_9 b(0)=bin X”0”X”0” 4 4 en bout init ld rst clk D(0) b(2) b(1) minus rst init clk set DFF 4-digit BCD Counter Down BCD_CD clk rst CD_mod_9 – Counter Down mod 9 bin – borrow in bout – borrow out minimum minimum = 1  Counter = dir minus dir minus dir minus dir minus dir = 0 : count down dir = 1 : count up

Result Storage & Processing - RSP en clk rst 13 REG en clk rst 13 REG en clk rst 13 REG en clk rst 13 REG store result last MAX ABS max MIN ABS min output 13 sel_out min maxlast result clk rst MAXABS – Maximum Absolute Value MINABS – Minimum Absolute Value

BTNL BTNS Debouncer RED clear Debouncer RED rst clk rst clk BTNR Debouncer RED next_out rst clk rst clk rst clk rst clk BUTTON_UNIT BTNU Debouncer RED store rst clk rst clk BTND Debouncer RED skip rst clk rst clk start_stop

CLOCK BTNL CLK_RST_4 BTND rst clk

Top-Level of Fast Reflex Game CU_mod_N: Counter Up mod N

Part 5 Demos of Lab 4 & Late Demos of Lab 3