Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 6: September 19, 2011 Restoration

Today How do we make sure logic is robust –Can assemble into any (feed forward) graph –Can tolerate voltage drops and noise –….while maintaining digital abstraction Penn ESE370 Fall DeHon 2

Outline Two problems Cascade failure Restoration Transfer Curves Noise Margins Non-linear Penn ESE370 Fall DeHon 3

Two Problems 1.Output not go to rail –Stops short of Vdd or Gnd 2.Signals may be perturbed by noise V x = V ideal ± V noise Penn ESE370 Fall DeHon 4

Output not go to Rail CMOS, capacitive load –Mostly doesn’t have problem CMOS, resistive load? Penn ESE370 Fall DeHon 5

Output not go to Rail Consider: –Vdd=1V –Vin=Gnd (both inputs) –R on (PMOS) = 500Ω –R load = 10KΩ What is Vout? –How close to rail do I need to get? Penn ESE370 Fall DeHon 6 R on =500 Ω R load =10K Ω R on =500 Ω

Wire Resistance Penn ESE370 Fall DeHon 7 Last Monday: R wire =10Ω

Wire Resistance 1000  m long wire? 1 cm long wire? Length of die side? Penn ESE370 Fall DeHon 8

Die Sizes Penn ESE370 Fall DeHon 9 ProcessorDie SizeTransistor CountProcess Core 2 Extreme X mm²291 Mio.65 nm Core 2 Duo E mm²291 Mio.65 nm Core 2 Duo E mm²291 Mio.65 nm Core 2 Duo E mm²167 Mio.65 nm Core 2 Duo E mm²167 Mio.65 nm Pentium D mm²376 Mio.65 nm Athlon 64 FX mm²227 Mio.90 nm Athlon mm²154 Mio.90 nm

Implications What does the circuit really look like for an inverter in the middle of the chip? Penn ESE370 Fall DeHon 10

Implications What does the circuit really look like for an inverter in the middle of the chip? Penn ESE370 Fall DeHon 11 Rwire Rrest_of_chip

IR-Drop Since interconnect is resistive and gates pull current off the supply interconnect –The Vdd seen by a gate is lower than the supply Voltage by V drop =I supply x R distribute –Two gates in different locations See different R distribute Therefore, see different V drop Penn ESE370 Fall DeHon 12 R rest_of_chip

Output not go to Rail CMOS, capacitive load  no problem CMOS, resistive load  voltage divider Due to IR drop, “rails” for two communicating gates may not match Penn ESE370 Fall DeHon 13

Two Problems 1.Output not go to rail –Is this tolerable? 2.Signals may be perturbed by noise –Voltage seen at input to a gate may not lower/higher than input voltage Penn ESE370 Fall DeHon 14

Noise Sources? What did we see in lab when zoomed in on signal transition? Signal coupling –Crosstalk Leakage Ionizing particles IR-drop in signal wiring Penn ESE370 Fall DeHon 15

Signals will be degraded 1.Output not go to rail –Is this tolerable? 2.Signals may be perturbed by noise –Voltage seen at input to a gate may not lower/higher than input voltage What happens to degraded signals? Penn ESE370 Fall DeHon 16

Preclass All 1’s  logical output? Penn ESE370 Fall DeHon 17

Preclass 1.0 inputs, gate: o=1-AB  output voltage? Penn ESE370 Fall DeHon 18

Preclass 0.95 inputs, gate: o=1-AB  output voltage? Penn ESE370 Fall DeHon 19

Degradation Cannot have signal degrade across gates Want to be able to cascade arbitrary set of gates Penn ESE370 Fall DeHon 20

Gate Creed Gates should leave the signal “better” than they found it –“better”  closer to the rails Penn ESE370 Fall DeHon 21

Restoration Discipline Define legal inputs –Gate works if Vin “close enough” to the rail Restoration –Gate produces Vout “closer to rail” This tolerates some drop between one gate and text (between out and in) Call this our “Noise Margin” Penn ESE370 Fall DeHon 22

Noise Margin V oh – output high V ol – output low V ih – input high V il – input low NM h = V oh -V ih NM l = V ol -V il Penn ESE370 Fall DeHon 23 One mechanism, addresses numerous noise sources.

Restoration Discipline (getting precise) Define legal inputs –Gate works if Vin “close enough” to the rail –Vin > V ih or Vin < V il Restoration –Gate produces Vout “closer to rail” Vout V oh Penn ESE370 Fall DeHon 24 Note: don’t just say V in >V ih  V out >V oh

Transfer Function Penn ESE370 Fall DeHon 25 What gate is this?

Restoring Transfer Function Penn ESE370 Fall DeHon 26

Restoring Transfer Function Penn ESE370 Fall DeHon 27 V il, V ih = slope -1 points V oh =f(V il ) V ol =f(V ih )

Restoring Transfer Function Penn ESE370 Fall DeHon 28 For multi-input functions, should be worst case. i.e. hold non-controlling inputs at Vil, Vih respectively. (relate preclass exercise)

Ideal Transfer Function Penn ESE370 Fall DeHon 29

Linear Transfer Function? O=Vdd-A Penn ESE370 Fall DeHon 30 Noise Margin?

Linear Transfer Function? Consider two in a row (buffer) O1=Vdd-A What is transfer function to buffer output O2? O2=(Vdd-O1) = Vdd-(Vdd-A)=A Penn ESE370 Fall DeHon 31

Linear Transfer Function? For buffer: O2=A Consider chain of buffers What happens if A drops a bit between each buffer? A i+1 = A i -Δ Penn ESE370 Fall DeHon 32 Conclude: Linear transfer functions do not provide restoration.

Non-linearity Need non-linearity in transfer function Could not have built restoring gates with –R, L, C circuit –Linear elements Penn ESE370 Fall DeHon 33

Transistor Non-Linearity Penn ESE370 Fall DeHon 34

All Gates If we hope to assemble design from collection of gates, –Voltage levels must be consistent and supported across all gates –Must adhere to a V il, V ih, V ol, V oh that is valid across entire gate set Penn ESE370 Fall DeHon 35

Admin Wednesday in Ketterer –Lab combo –Read through HW2 –Be ready to run electric and spice on linux CETS machines own laptop that you bring with you Friday back here Penn ESE370 Fall DeHon 36

Big Idea Need robust logic –Can assemble into any (feed forward) graph –Can tolerate loss and noise –….while maintaining digital abstraction Restoration and noise margins –Every gate makes signal “better” –Design level of noise tolerance Penn ESE370 Fall DeHon 37