An Abstract Model of De- synchronous Circuit Design and Its Area Optimization Jin Gang University of Manchester.

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Presentation transcript:

An Abstract Model of De- synchronous Circuit Design and Its Area Optimization Jin Gang University of Manchester

Overview Motivation Design flow Abstract model － Control Graph Timed Petri-net model for Control Path Performance Evaluation Area Optimization Conclusion

Motivation Asynchronous Circuit –Benefit Low power Better EMC Modularity –Drawback Difficult to design

Motivation De-synchronous Circuit –Benefit Benefit from Asynchronous Design within synchronous design tools –Drawback Not the original asynchronous design method May introduce some area overhead into circuit

Design Flow Datapath design is the same as synchronous counterpart More concern need to give to the control path

Design Flow 1. Split each flip-flop into a master-slave latch pair. 2. Generate the matched delay unit for each combinational logic path. 3. Implement the local controller corresponding to each latch.

Control Graph An abstract model for control path Use a directed graph to represent the control path Purpose of this model –Evaluate the performance of the circuit –Optimize the circuit

Control Graph

Timed Petri-net model for control path A Timed Petri-net model for control path can be derived from control graph

Performance Evaluation Use the average cycle time to evaluate the performance of the de-synchronous circuit The performance evaluation is a linear programming problem

Area Optimization Multi local controllers can be combined to a single local controller Condition –Only the local controllers with same polarity can be combined –This combination can preserve the equality of the circuit

Area Optimization

This optimization problem is NP-hard The optimizing procedure need be directed by the performance evaluation function, which can grantee the performance of the circuit This optimization is a trade-off between the area and the benefit of asynchronous circuit

Area Optimization Θ is the a threshold defined to control the maximal number of the latches can driven by a single local controller After the optimization, the fan-in and fan- out of the control path will be changed, so the area also will be changed according it

Results Θ=2 OriginalOptimized CircuitVertexEdgeC-elementVertexEdgeC-element s s s s s s s s s

Results Θ=3 OriginalOptimized CircuitVertexEdgeC-elementVertexEdgeC-element s s s s s s s s s

The change of average fan-in and fan-out OriginalOptimized CircuitAverage fan-in/outAverage fan-in/out(Θ=2)Average fan-in/out(Θ=3) s s s s s s s s s

Conclusion Compatible with synchronous design method Can reduce the area overhead of the control path Can preserve the performance of the circuit Will lose some benefit of asynchronous circuit

Finish Thanks for your attention