Slide 4-1 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 4 Computer Organization

Slide 4-2 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The Von Neumann architecture

Slide 4-3 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Stored Program Computers and Electronic Devices Patter n Fixed Electronic Device Variable Program Stored Program Device Jacquard Loom

Slide 4-4 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Program Specification int a, b, c, d;... a = b + c; d = a - 100; Source ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a load R4,=100 subtract R3,R4 store R3,d Assembly Language

Slide 4-5 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Machine Language ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a load R4,=100 subtract R3,R4 store R3,d Assembly Language … … … … … … …1 Machine Language

Slide 4-6 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The von Neumann Architecture Control Unit (CU) Central Processing Unit (CPU) Device Address Bus Data Bus Arithmetical Logical Unit (ALU) Primary Memory Unit (Executable Memory)

Slide 4-7 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The ALU R1 R2 Rn... Status Registers Functional Unit Left Operand Right Operand Result To/from Primary Memory load R3,b load R4,c add R3,R4 store R3,a

Slide 4-8 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Control Unit Primary Memory Fetch Unit Decode Unit Execute Unit PC IR Control Unit load R3,b load R4,c add R3,R4 store R3,a … … … …1 load R4, c 3050

Slide 4-9 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Control Unit Operation PC = ; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; // fetch phase }; Fetch phase: Instruction retrieved from memory Execute phase: ALU op, memory data reference, I/O, etc.

Slide 4-10 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Primary Memory Unit MAR MDR Command n Read Op: Load MAR with address read 2. Load Command with “read” Data will then appear in the MDR

Slide 4-11 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 A Pipelined Function Unit Function Unit Operand 1 Operand 2 Result Operand 1 Operand 2 Result (a) Monolithic Unit (b) Pipelined Unit

Slide 4-12 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 A SIMD Machine ALU Control Unit ALU Control Unit ALU … (a) Conventional Architecture (b) SIMD Architecture

Slide 4-13 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 I/O Devices

Slide 4-14 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The Device-Controller-Software Relationship Application Program Device Controller Device Software in the CPU Abstract I/O Machine Device manager Program to manage device controller Supervisor mode software

Slide 4-15 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Device Controller Interface Command Status Data 0 Data 1 Data n-1 Logic busydoneError code... busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined)

Slide 4-16 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Performing a Write Operation while(deviceNo.busy || deviceNo.done) ; deviceNo.data[0] = deviceNo.command = WRITE; while(deviceNo.busy) ; deviceNo.done = TRUE; Devices much slower than CPU CPU waits while device operates Would like to multiplex CPU to a different process while I/O is in process It is called a spin-lock

Slide 4-17 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Direct Memory Access Primary Memory CPU Controller Device Primary Memory CPU Controller Device

Slide 4-18 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Addressing Devices Primary Memory Device 0 Device 1 Device n-1 Primary Memory Device 0 Device 1 Device n-1 Device Addresses Memory Addresses

Slide 4-19 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Interrupts

Slide 4-20 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Detecting an Interrupt CPU Device InterruptRequest flag

Slide 4-21 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Control Unit with Interrupt (Hardware) while(haltFlag not SET) { IR = memory[PC]; execute(IR); PC = PC + 1; if(InterruptRequest) { memory[0] = PC; PC = memory[1] }; memory[1] contains the address of the interrupt handler

Slide 4-22 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Interrupt Handler (Software) interruptHandler() { saveProcessorState(); for(i=0; i<NumberOfDevices; i++) if(device[i].done) goto deviceHandler(i); /* something wrong if we get to here … */ deviceHandler(int i) { finishOperation(); returnToScheduler(); }

Slide 4-23 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Disabling Interrupts if(InterruptRequest && InterruptEnabled) { /* Interrupt current process */ disableInterrupts(); memory[0] = PC; PC = memory[1]; }

Slide 4-24 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 CPU-I/O Overlap CPU Device … Ready Processes CPU Device … Ready Processes I/O Operation CPU Device … Ready Processes Uses CPU

Slide 4-25 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 Software interrupts (traps, system calls)

Slide 4-26 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The trap Instruction (Hardware) executeTrap(argument) { setMode(supervisor); switch(argument) { case 1: PC = memory[1001]; // Trap handler 1 case 2: PC = memory[1002]; // Trap handler 2... case n: PC = memory[1000+n];// Trap handler n }; The trap instruction dispatches a trap handler routine atomically Trap handler performs desired processing “A trap is a software interrupt”

Slide 4-27 Copyright © 2004 Pearson Education, Inc. Operating Systems: A Modern Perspective, Chapter 4 The Trap Instruction Operation S Mode Trusted Code trap UserSupervisor Branch Table 2 31