DPPM for Analog and RF Circuits Vishwani D. Agrawal Auburn University, Auburn, AL 36849, USA Suraj Sindia Intel Corporation, Hillsboro,

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Presentation transcript:

DPPM for Analog and RF Circuits Vishwani D. Agrawal Auburn University, Auburn, AL 36849, USA Suraj Sindia Intel Corporation, Hillsboro, OR 97124, USA 32nd IEEE VLSI Test Symposium Napa, California April 14, 2014

Problem Statement Given: – A set of complete specification-based tests for an analog or RF circuit, and – An acceptable defect level (DL), Find the smallest set of tests that should be used. 3/13/2014LATW 2014: Spec. Test Minimization2

A Bipartite Graph 3/13/2014LATW 2014: Spec. Test Minimization3 T2T2 T3T3 T1T1 T4T4 S1S1 S2S2 S3S3 S4S4 p 11 p 22 p 33 p 44 p 34 p 42 p 12 p 21 p 13 Tests Specifications

Operational Amplifier: TI LM741 3/13/2014LATW 2014: Spec. Test Minimization4

Test Minimization 3/13/2014LATW 2014: Spec. Test Minimization5 DL PPM ILP solution Tests selected Test size reduction x1x1 x2x2 x3x3 x4x4 x5x5 x6x6 x7x % % % 1, % 10, %

Conclusion Specification tests are given. Monte Carlo spice simulation determines probability, p ij, of ith test checking for jth specification. An integer linear program (ILP) determines the defect level for any number of tests. References: – S. Sindia and V. D. Agrawal, “Specification Test Minimization for Given Defect Level,” Proc. 15th IEEE Latin-American Test Workshop, Fortaleza, Brazil, March 13, – A detailed paper submitted to ITC /13/2014LATW 2014: Spec. Test Minimization6