2/16/2016 Chapter Four Array Computers Index Objective understand the meaning and structure of array computer realize the associated instruction sets,

Slides:



Advertisements
Similar presentations
Chapter 2: Data Manipulation
Advertisements

Machine cycle.
Chapter 1. Basic Structure of Computers
Programming Languages Marjan Sirjani 2 2. Language Design Issues Design to Run efficiently : early languages Easy to write correctly : new languages.
Vector Processing. Vector Processors Combine vector operands (inputs) element by element to produce an output vector. Typical array-oriented operations.
Parallell Processing Systems1 Chapter 4 Vector Processors.
Computer Architecture and Data Manipulation Chapter 3.
William Stallings Computer Organization and Architecture 9th Edition
Computer Organization. This module surveys the physical resources of a computer system. –Basic components CPUMemoryBus I/O devices –CPU structure Registers.
1 Introduction to Data Parallel Architectures Sima, Fountain and Kacsuk Chapter 10 CSE462.
Copyright © 2008 Pearson Education, Inc. Publishing as Pearson Addison-Wesley Computer Science: An Overview Tenth Edition by J. Glenn Brookshear Chapter.
Advanced Topics in Algorithms and Data Structures An overview of the lecture 2 Models of parallel computation Characteristics of SIMD models Design issue.
Data Parallel Algorithms Presented By: M.Mohsin Butt
\course\eleg652-03F\Topic1a- 03F.ppt1 Vector and SIMD Computers Vector computers SIMD.
ELEC 6200, Fall 07, Oct 29 McPherson: Vector Processors1 Vector Processors Ryan McPherson ELEC 6200 Fall 2007.
Models of Parallel Computation Advanced Algorithms & Data Structures Lecture Theme 12 Prof. Dr. Th. Ottmann Summer Semester 2006.
Chapter 2: Impact of Machine Architectures What is the Relationship Between Programs, Programming Languages, and Computers.
Elements of the Computer (How a processor works)
Structured Data Types and Encapsulation Mechanisms to create new data types: –Structured data Homogeneous: arrays, lists, sets, Non-homogeneous: records.
Introduction to Parallel Processing Ch. 12, Pg
Chapter 5 Array Processors. Introduction  Major characteristics of SIMD architectures –A single processor(CP) –Synchronous array processors(PEs) –Data-parallel.
Basic Operational Concepts of a Computer
Course Outline Introduction in software and applications. Parallel machines and architectures –Overview of parallel machines –Cluster computers (Myrinet)
Computer Organization Computer Organization & Assembly Language: Module 2.
COT 4600 Operating Systems Spring 2011 Dan C. Marinescu Office: HEC 304 Office hours: Tu-Th 5:00 – 6:00 PM.
Anshul Kumar, CSE IITD CS718 : Data Parallel Processors 27 th April, 2006.
Multiprocessor systems Objective n the multiprocessors’ organization and implementation n the shared-memory in multiprocessor n static and dynamic connection.
Pipeline And Vector Processing. Parallel Processing The purpose of parallel processing is to speed up the computer processing capability and increase.
Operating Systems Lecture 02: Computer System Overview Anda Iamnitchi
CHAPTER 12 INTRODUCTION TO PARALLEL PROCESSING CS 147 Guy Wong page
Chapter 2 Parallel Architecture. Moore’s Law The number of transistors on a chip doubles every years. – Has been valid for over 40 years – Can’t.
Chapter 1 Introduction. Objectives To explain the definition of computer architecture To discuss the history of computers To describe the von-neumann.
PIPELINING AND VECTOR PROCESSING
High Performance Fortran (HPF) Source: Chapter 7 of "Designing and building parallel programs“ (Ian Foster, 1995)
Chapter 9: Alternative Architectures In this course, we have concentrated on single processor systems But there are many other breeds of architectures:
© 2005 Pearson Addison-Wesley. All rights reserved Figure 2.1 This chapter focuses on key hardware layer components.
ELEN 033 Lecture #1 Tokunbo Ogunfunmi Santa Clara University.
Chapter 2 Data Manipulation © 2007 Pearson Addison-Wesley. All rights reserved.
Computer Science 101 Computer Systems Organization.
Chapter 2 Data Manipulation. © 2005 Pearson Addison-Wesley. All rights reserved 2-2 Chapter 2: Data Manipulation 2.1 Computer Architecture 2.2 Machine.
Copyright © 2008 Pearson Education, Inc. Publishing as Pearson Addison-Wesley Data Manipulation Brookshear, J.G. (2012) Computer Science: an Overview.
Chapter 2 Data Manipulation © 2007 Pearson Addison-Wesley. All rights reserved.
Vector and symbolic processors
Chapter 2 Data Manipulation © 2007 Pearson Addison-Wesley. All rights reserved.
A Level Computing for AQA Teacher’s Resource CD-ROM 4 CHAPTER: Functional characteristics of a processor.
Chapter 2: Data Manipulation
Question What technology differentiates the different stages a computer had gone through from generation 1 to present?
Parallel Algorithms for array processors
Chapter 2 Data Manipulation © 2007 Pearson Addison-Wesley. All rights reserved.
Array computers. Single Instruction Stream Multiple Data Streams computer There two types of general structures of array processors SIMD Distributerd.
F453 Module 8: Low Level Languages 8.1: Use of Computer Architecture.
A computer consists of five functionally independent main parts.
© 2015 Pearson Education Limited 2015 Quiz in last 15 minutes Midterm 1 is next Sunday Assignment 1 due today at 4pm Assignment 2 will be up today; due.
CHAPTER SEVEN PARALLEL PROCESSING © Prepared By: Razif Razali.
Distributed Processors
Chapter 4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures Topic 13 SIMD Multimedia Extensions Prof. Zhang Gang School.
How does an SIMD computer work?
Parallel and Multiprocessor Architectures
Array Processor.
Functional Units.
Multivector and SIMD Computers
Chapter 2: Data Manipulation
Chapter 2: Data Manipulation
COMPUTER ARCHITECTURES FOR PARALLEL ROCESSING
Chapter 2: Data Manipulation
Presentation transcript:

2/16/2016 Chapter Four Array Computers

Index Objective understand the meaning and structure of array computer realize the associated instruction sets, interprocessor communication etc. manifest the direction of array computers

Index Historic background SOLOMON and ILLIAC Burroughs Scientific Processor - capable of performing 50 MFLOP STARAN resides in 32 array modules each of which contains 256 PEs. ICL DAP is an SIMD having a total of 4096 processors in a 64 x 64 matrix.

Index Terminology AE –Arithmetic elements AP –Arithmetic processors AM –Array memory CP Control processor. The control unit

Index Characteristics of a processor array A regular lattice of processors in one or more dimensions Most of the processors in SIMD computer are simple in its structure Each processor has access to a block of a local memory Each processor has data connections to its nearest neighbours. At a given moment all processors execute the same instruction

Index Organization of an array computer ILLIAVC is the machine that utilizes the approach of array processor. The arithmetic processors execute the instructions making use of their local memories. Control unit.

Index Control Unit & AP

Index Communications amongst processor arrays Complete connection network Cyclically connected

Index Complete connection

Index Cyclic Connection

Index Memory access mechanism deals with problems of accessing the shared memory by the arithmetic processors. If the memory is blocked because it is used by other arithmetic processor. The processor has to wait until it is released.

Index Straight Storage Place the memory cell as it is.

Index Skewed storage Skewed storage means the shift of storage cell.

Index Array computers in perspective The computation must be describable by vector instructions High-speed data routing between processors must be possible Operands to be manipulated simultaneously must be capable of being fetched simultaneously The future approach for array processors is to increase their flexibility while retaining their efficiency for vector computations.

Index Summary array computer is formed by a single control unit and a number of arithmetic processors. Array computer is an example of SIMD model The arithmetic processors are linked up through a communication network. Each processor can access the memory storage locally or through the network.