doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 1 Scrambler Mismatch Correction Using the MAC FEC Mark Webster, Mike Seals, Steve Halford, Paul Chiuchiolo Intersil July 2002

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 2 Overview A forward-error-correction (FEC) option exists in the e draft which uses an 8-octet correcting Reed- Solomon (255,239) block code. If the a PHY demodulator makes any bit-errors in the received scrambler seed (state), the FEC blocks will all error. (IEEE /050 and –02/221) An nice solution to this problem has been proposed (IEEE /325) Unfortunately, this solution weakens the performance of the Reed-Solomon FEC Herein, a simple technique is presented which restores a performance to frame-error-rates No additional overhead is added to the FEC frames to make this technique work The FEC is used to help determine the scrambler mismatch

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 3 Solution Constraints The MAC and PHY cannot coordinate. The existing interface must remain as is. The fix cannot be made in the PHY Systematic property must remain, so e radios w/o the FEC option can process PHY-error-free frames Legacy radio’s (pre e) must be able to read the MAC header without any knowledge of e

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 4 Desirable Solution Features Works at frame-error-rates to (IEEE /40 and /377) Works for short frames and long frames Introduces no extra frame overhead Solution works for all PHY’s –Prevents MAC from being PHY dependent –Must fix the a problem (and g’s OFDM) –Must not introduce a new problem to other PHY’s –The MAC-level fix should be PHY blind Low complexity, low latency, little buffering

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide e FEC Frame Format to MAC Header Variable Length Frame Body Frame Checksum FEC Parity Octets MAC Header FEC Block: (48,32) shortened by m = 207 Normal Data FEC Block: (224,208) shortened by m = 31 All numbers are in octets

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 6 An Existing Proposed Solution

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 7 A Proposed Solution Presented in Sydney, May 2002 –Doc.: IEEE /325r0 –Title: Dual Precoding with FEC Packets –Authors: Chris Heegard, Lior Ophir, Richard Williams and Sid Schrum Moving average bit-filters and recursive bit-filters are used, exploiting the properties of the a scrambler mismatch sequence

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 8 Solution Presented in Sydney (doc:IEEE /325r0) 1/g(D) IIR x(D) FEC Encode g(D) FIR 1/g(D) IIR + x 2 (D)=0 1/g(D) IIR FEC Decode g(D) Self-Sync FIR x(D) Equivalent a PHY Legacy Stations See Systematic Data (MAC Header) Scrambler Mismatch Removed Initial state No mismatch: state =0 Mismatch: state ~=0

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 9 Issues With Sydney’s Solution Precoding weakens the MAC FEC (IEEE r3-E) The receive self-synchronizing FIR filter causes error multiplication –Up to 3 * (Number of bit errors) –Up to 2 * (Number of octet errors) Instead of the Reed-Solomon (255,239) correcting 8 octets in error, it can be limited by 4 octets in error at the PHY output The FEC effectiveness is lower-bounded to half the design goal for independent octet errors

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 10 Bit-Error Multiplication Problem D4D4 D3D3 ++ FIR Bit-Filter, g(D) Input Bit Error Pattern Output Bit Error Pattern One input error 3 output errors For every input bit error, up to 3 output bits errors can occur. RX PHY OUTPUTTO FEC DECODER

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 11 Octet-Error Multiplication Problem D4D4 D3D3 ++ FIR Bit-Filter, g(D) Input Octet Error Pattern Output Bit Error Pattern One octet in error 2 octets in error For every input octet in error, up to 2 output octets can be in error. TO FEC DECODERX PHY OUTPUT

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 12 PHY Error Events 1 and 2 Mbps DSSS & FH PHY’s experience random bit errors 5.5 Mbps CCK experiences nibble errors (4 bit chunks) 11 Mbps CCK experiences octet errors OFDM experiences some form of error clustering due to Viterbi trace-back re- sync behavior

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 13 A New Idea

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 14 A New Idea MAC header is short compared to full FEC blocks (32 vs. 208 data octets), so the MAC header is much more robust. Therefore, use dual-precoding on the MAC header only. Dual-precoding enables FEC decoding in the face of scrambler mismatch The FEC can then be used to help compute the scrambler mismatch

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 15 New Solution’s Frame Format Use dual precoding only on the MAC header –Little performance loss because MAC header is so short No additional overhead added to frame to MAC Header Variable Length Frame Body Frame Checksum Correct scrambler mismatch Switch to pure FEC Do not use precoding here Use dual precoding MAC computes scrambler mismatch

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 16 New Solution’s Block Diagram 1/g(D) IIR FEC Encode g(D) FIR 1/g(D) IIR FEC Decode g(D) Self-Sync FIR PHYPHY x(D) MUXMUX MUXMUX FEC Encode MUXMUX MUXMUX FEC Decode x(D) Compute Scrambler Mismatch Tx MUX Control MAC HDR Blk: Upper Path Data Blk: Lower Path Rx MUX Control MAC HDR Blk: Upper Path Data Blk: Lower Path + Scrambler Correct Jam State

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 17 Computing Scrambler Mismatch: Basic Concept x(D)+  (D)+E(D) + Desired Data Scrambler Mismatch Noise Bit Errors  (D)+E(D) Strip Data + Strip Errors  (D) x(D)E(D) PHY Any 7 error-free bits specify state. Location specifies state phase offset. Provided by FEC Decoder Only exists for a Recovered Data Error Pattern

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 18 Compute Scrambler Mismatch Using MAC Header 1/g(D) IIR FEC Decode g(D) Self-Sync FIR Rx Data x(D) PHY x(D)+  (D)+E(D) + Desired Data Scrambler Mismatch Bit Errors  (D)+E(D) Strip Data 1/g(D) IIR Trimmed g(D)E(D) + Strip Errors Trim Input To Start at Zero State Jam Error Pattern State=0  (D) Unique State Any 7 error-free bits (address) Plus, location in frame (index) g(D)x(D) +  (D) +g(D)E(D) Recovered Data g(D)x(D) Scrmblr Mismatch State  (D): Self-Sync start-up errors. Occur only in first 7 bits. (first octet). Error Pattern  (D)+g(D)E(D) Trimmed E(D)

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 19 Performance with a Performance reaches frame error rates No degradation with 7 FEC payload blocks Small degradation with 1 FEC payload block Error Rate vs. Bit SNR

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 20 Performance with b (mandatory modes) Uncorrelated octet errors Some performance loss exists if used on low-error-rate b packets Some MAC implementations may choose to not be PHY blind? Error Rate vs. Byte Error Rate

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 21 Additional Detail

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 22 FEC Decoder Detail Error pattern is easily output from FEC decoder Error Pattern  (D)+g(D)E(D)

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 23 Recovering Bit Errors E(D): Linear Superposition g(D) Self-Sync FIR PHY 1/g(D) IIR g(D)E(D) E(D) IIR state must match FIR state IIR is not self-synchronizing IIR state must not contain false errors IIR has infinite false-error propagation It will be shown how to do this In practice, Provided by FEC decoder 1 st octet is discarded to eliminate self-sync start-up errors  (D) Bit Errors

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 24 Example: Trim Error Pattern and Jam IIR State g(D) Self-Sync FIR PHY Error Pattern provided by FEC Decoder … At this point trim-off precursor. g(D) is error-flushed with probability = 1 Trim Input To Start at Zero State 1/g(D) IIR Jam Error Pattern State= … Trimmed E(D)

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 25 Trim Error Pattern and Jam IIR State to Zero 8 octets in error maximum at FEC input, so 48 – 8 = 40 octets in MAC header are not in error Min-Max separation between FEC-input error octets is 48/8 = 6 octets. Therefore, >= 5 sequential octets are not in error in any given MAC header. Therefore, FEC-input error pattern always has a straight of 5*8 = 40 bit-zeros or longer At the end of 40 bits of zeros at FEC input, the self-sync FIR has been flushed (state=0) with essentially probability = 1 –Jam IIR to same state (state=0) and start injecting error pattern into IIR filter at this point Only a PHY-output bit-error pattern which matches the scrambling sequence can spoof this. But, if this occurs the bit-error-rate is nearly 50%, and the octet error rate is 100%. The spoof can only occur on frames impossible to FEC decode. Spoof rate rate << 2 -40

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 26 Example Where g(D) Flush Event is Spoofed (<< event) (Matches scrambling pattern) PHY Output Thermal Bit-Error-Pattern g(D) Self-Sync FIR PHY (Provided by FEC Decoder) FEC-Input Bit-Error-Pattern FEC Decode But, G(d) is never flushed Of errors It appears g(D) FIR Is flushed of errors Thermal bit-error-rate is 50% Thermal octet-error-rate is 100% g(D)E(D) E(D)

doc.: IEEE /429r0 Submission July 2002 Mark Webster, IntersilSlide 27 Conclusion This submission has described a technique for restoring the full performance of the e FEC in the face of a scrambler mismatch No additional overhead is used The technique is simple to implement