Survey of Reconfigurable Logic Technologies ECE 448 Lecture 11 Survey of Reconfigurable Logic Technologies ECE 448 – FPGA and ASIC Design with VHDL
Resources Xcell Journal available for FREE on line or in the printed form @ http://www.xilinx.com/publications/xcellonline/ FPGA and Structured ASIC Journal available for FREE by e-mail or on the web @ http://www.fpgajournal.com/ ECE 448 – FPGA and ASIC Design with VHDL
Technology Timeline ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Programmable Logic Devices ECE 448 – FPGA and ASIC Design with VHDL
First Programmable Logic Devices The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Programmable logic device as a black box Logic gates and programmable switches Inputs (logic variables) Outputs (logic functions) ECE 448 – FPGA and ASIC Design with VHDL
General structure of a PLA (Programmable Logic Array) x x x 1 2 n Input buffers & inverters x x x x 1 1 n n P 1 AND plane OR plane P k f f 1 m ECE 448 – FPGA and ASIC Design with VHDL
Gate-level diagram of a PLA x x x 1 2 3 Programmable connections OR plane P 1 P 2 P 3 P 4 AND plane f 1 f 2 ECE 448 – FPGA and ASIC Design with VHDL
Customary schematic for a PLA 1 P 2 x 3 OR plane AND plane 4 ECE 448 – FPGA and ASIC Design with VHDL
Programmable Array Logic f 1 P 2 x 3 AND plane 4 ECE 448 – FPGA and ASIC Design with VHDL
Macrocell at the output of PAL 1 To AND plane D Q Clock Select Enable Flip-flop ECE 448 – FPGA and ASIC Design with VHDL
A generic structure of CPLD (Complex Programmable Logic Device) The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Structure of a CPLD Interconnection wires I/O block PAL-like block ECE 448 – FPGA and ASIC Design with VHDL
A section of a CPLD ECE 448 – FPGA and ASIC Design with VHDL D Q PAL-like block ECE 448 – FPGA and ASIC Design with VHDL
Connections between the programmable interconnect matrix and simple PAL-like blocks The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Field Programmable Gate Arrays ECE 448 – FPGA and ASIC Design with VHDL
General structure of an FPGA The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Xilinx CLB ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Simplified view of a Xilinx Logic Cell The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
RAM Blocks and Multipliers in Xilinx FPGAs The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Embedded Microprocessor Cores The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Virtex-II Pro Architecture 2 4 6 1 5 3 Features: Processor Block RocketIO Multi-Gigabit Transceivers CLB and Configurable Logic SelectIO-Ultra Digital Clock Managers Multipliers and Block SelectRAM ECE 448 – FPGA and ASIC Design with VHDL
ECE 448 – FPGA and ASIC Design with VHDL
Processor Block Contains four components: Embedded IBM PowerPC 405-D5 RISC CPU core On-Chip Memory (OCM) controllers and interface Clock/control interface logic CPU-FPGA Interfaces IBM CoreConnect Bus Architecture Features: Processor Local Bus (PLB) On-chip Peripheral Bus (OPB) Device Control Register (DCR) Bus BRAM BRAM Control OCM Controller PPC 405 Core FPGA CLB Array OCM Controller Interface Logic BRAM BRAM ECE 448 – FPGA and ASIC Design with VHDL
PowerPC Cores ECE 448 – FPGA and ASIC Design with VHDL PowerPC System
Embedded Development Kit (EDK) Hardware Flow Software Flow Processor IP, Microprocessor Peripheral Description Files VHDL / Verilog C / C++ Code Libraries PlatGen Synthesizer Compiler LibGen Microprocessor Hardware Specification File Microprocessor Software Specification File EDIF IP Netlists Object Files ISE / Xflow System Constraint File Linker Bitstream Data2MEM Executable Download to FPGA ECE 448 – FPGA and ASIC Design with VHDL
A simple clock tree ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Clock Manager ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Jitter ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Removing Jitter ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Frequency Synthesis ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Phase shifting Figure 4-20 ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Figure 4-20 ECE 448 – FPGA and ASIC Design with VHDL
Removing Clock Skew ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
General-Purpose IO Blocks The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Using High-Speed Tranceivers to Communicate Between Devices The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Programming Reconfigurable Logic Devices ECE 448 – FPGA and ASIC Design with VHDL
A Fusible Link Technologies: Unprogrammed Device The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
A Fusible Link Technologies: Programmed Device The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
An Antifuse Technology: Unprogrammed Device The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
An Antifuse Technology: Programmed Device The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Growing an Antifuse ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
EPROM Technology ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
An EPROM Transistor-Based Memory Cell The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
EEPROM Technology ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Static RAM-based Technology The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Summary of Programming Technologies The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
SRAM FPGA Configuration Loading the bitstream into internal memory by delivering it through one of the configuration interfaces Configuration phases: Clearing the configuration memory Initialization Bitstream loading Device startup JTAG SelectMAP Slave/Master Serial ICAP Correspond to configuration modes Configuration Device SRAM FPGA Bitstream Configuration Interface 101110101011100101001010011101 A series of command and data Configuration Logic Configuration Memory ECE 448 – FPGA and ASIC Design with VHDL
Configuration of SRAM based FPGAs The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
FPGA Configuration Modes The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Serial Load with FPGA as a Master The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Daisy-Chaining FPGAs ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Parallel Load with FPGA as a Master (off-the-shelf memory) The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Parallel Load with FPGA as a Master (special-purpose memory) The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Parallel Load with FPGA as a Slave The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Using the JTEG Port JTEG = Joint Test Action Group, IEEE 1149.1 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Internal Processor Boundary Scan Chain The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) ECE 448 – FPGA and ASIC Design with VHDL
Reconfiguration Interfaces in Xilinx FPGAs Internal Port ICAP (Virtex-II) JTAG SelectMap (8 bits Parallel) ECE 448 – FPGA and ASIC Design with VHDL
Configuration times of selected FPGA devices ECE 448 – FPGA and ASIC Design with VHDL