2/1/20001 ECE 551: Digital System Design & Synthesis Lecture Set 7 7.1: Coding for if and case 7.2: Coding logic building blocks (In separate file) 7.3: High-Performance Coding (In separate file)

03/03/20032 ECE Digital System Design & Synthesis Lecture 7.1 Coding for Synthesis of Combinational Logic Overview  Premise  Basic coding for if and case  Synopsis case directives  Late signal arrival coding for if and case Data, Control  Coding Logic Building Blocks Decoder, Priority Encoder, Reduction XOR, Multiplexer  High-Performance Methods Datapath Duplication, Operator in if condition  General Coding Issues  Resource Sharing  Arithmetic Expression Optimization

03/03/20033 Premise  HDL coding influences the hardware implementations produced by synthesis  Affects figure of merit and tradeoff  FoM = delay x area  Delay/area tradeoff  Think hardware when coding!  Results are Synopsys specific!

03/03/20034 References  Synopsys, Guide to HDL Coding Styles for Synthesis, version , GHCS.  HDL Compiler for Verilog Reference Manual, version Chapter 8, HCVR.  Design Compiler User Guide, version Chapter 3, DCUG.  Can be referenced on CAE Unix: /afs/engr.wisc.edu/apps/eda/synopsys /doc/online/

03/03/20035 Basic Coding Using if and case  Example 1-1 GHCS  Multiplexer with multiple if’s  Figure 1-1 Resulting structure using SELECT_OP in cascade structure with effective priority encoding of selection.  Example 1-3 GHCS  Multiplexer with single if  Figure 1-2 Resulting structure using SELECT_OP and gates is “flattened,” but control that results is still priority encoded selection.  Example 1-5 GHCS  Uses casex to permit use of don’t cares in conditions  Control signals not priority encoded.

03/03/20036 Example 1-1 Verilog: Multiple Ifs

03/03/20037 Example 1-1 Circuit: Cascade  Note last statement has highest priority!  Long worst case delay for both data and control

03/03/20038 Example 1-3 Verilog: Single If

03/03/20039 Example 1-3 Circuit: Single Select – Priority Decode  Note first condition has highest priority!  Short delays

03/03/ Example 1-5 Verilog: Casex  Note use of casex and x’s to obtain optimized logic

03/03/ Example 1-5 Circuit: Single Select  Priority encoded – first condition has highest priority  Short delays

03/03/ Synopsys Case Directives  case (condition) // synopsys parallel_case  Eliminates the priority decoder  Selection lines go directly into Select Op  case (condition) // synopsys full_case  Declares that all “cases” are present  Prevents formation of latches

03/03/ Late Signal Arrival Coding for if and case - Data  Objective - force smaller delay to output from “late arriving” data signal(s).  Example 2-1 GHCS  Multiplexer with multiple if’s  Figure 2-1 Resulting structure using SELECT_OP in cascade structure with late arriving data b forced to output - priority encoding behavior preserved.

03/03/ Late-Arriving Data Verilog: Fixed  Original is Example 1-1: Late data b is far from output  Lateness of b and long logic delay add

03/03/ Late-Arriving Data Circuit: Fixed

03/03/ Late signal arrival coding for if and case - Control  Objective - force smaller delay to output from “late arriving” control signal(s).  Example 2-3 GHCS  Multiplexer with single if  Figure 1-2 Resulting structure similar using SELECT_OP with “flattened” priority control logic  Example 2-5 GHCS  Multiplexer with single if  Figure 2-2 Resulting structure is decomposition with late arrival control closest to output. Note that delays are reduced due to smaller SELECT_OP due to lower gate fan- in.

03/03/ Late-Arriving Control Verilog: Original  Original is Example 1-1: Late data b is far from output  Lateness of b and long logic delay add

03/03/ Late-Arriving Control Circuit: Fixed

03/03/ Late-Arriving Control Verilog: Fixed - 1

03/03/ Late-Arriving Control Verilog: Fixed - 2

03/03/ Late-Arriving Control Circuit: Fixed

03/03/ Late signal arrival coding for if with nested case - Data  Objective - force smaller delay to output from “late arriving” data signal(s).  Example 2-7 GHCS  Complex selector with single if with nested case  Figure 2-3 Resulting structure is cascaded SELECT_OP  Example 2-9 GHCS  Decomposition placing selection of late data near output  Figure 2-4 Resulting structure has late arriving data passing through single 2-way SELECT_OP

03/03/ Late-Arriving Data – If with Nested Case Verilog: Original - 1

03/03/ Late-Arriving Data – If with Nested Case Verilog: Original - 2

03/03/ Late-Arriving Data – If with Nested Case Circuit: Original - 2  Late-arriving data passes through two Select_Op’s

03/03/ Late-Arriving Data – If with Nested Case Verilog: Fixed - 1

03/03/ Late-Arriving Data – If with Nested Case Verilog: Fixed - 2

03/03/ Late-Arriving Data – If with Nested Case Circuit: Fixed  Late-arriving data enters last Select_Op

03/03/ Late signal arrival coding for case with nested if – Control  Objective - force smaller delay to output from “late arriving” control signal(s).  Example 2-11 GHCS  Complex selector with single case with nested if  Figure 2-5 Resulting structure is cascaded SELECT_OP  Example 2-13 GHCS  Decomposition placing selection of late data near output  Table 2-1 Resulting design has lower delay and lower area (better FoM)

03/03/ Late-Arriving Control – Case with Nested If Verilog: Original

03/03/ Late-Arriving Control – Case with Nested If Circuit: Original

03/03/ Late-Arriving Control – Case with Nested If Verilog: Fixed - 1

03/03/ Late-Arriving Control – Case with Nested If Verilog: Fixed - 2

03/03/ Late-Arriving Control – Case with Nested If Synth Data: Compare  Delay improved by 16%  Small area improvement

03/03/ Summary  Area and timing are coding dependent  Learn to visualize hardware that results from code  Priority decoding  Natural due to the sequential processing of statements  Often not needed, so in such cases:  Learn how to avoid it to save area and time  Delay control can be done through coding