Research Roadmap Past – Present – Future Robert Brayton Alan Mishchenko Logic Synthesis and Verification Group UC Berkeley

2 Overview Past work Past work Espresso Espresso SIS SIS MVSIS MVSIS Current work Current work ABC ABC Future work Future work present 5 25 Time, years

3 Past 25 Years Various adaptations of these tools still used extensively in commercial CAD Various adaptations of these tools still used extensively in commercial CAD Espresso (two-level synthesis) Binary and multi-valued SOP minimization, pair-decoding, disjoint covers, etc MIS-II (multi-level synthesis) Factoring, extracting shared logic, elimination, resubstitution, simplification, etc SIS (sequential multi-level synthesis) Don’t-cares, retiming, state-encoding, tech-mapping, asynchronous, etc SOPs SOPs BDDs

4 Logic Synthesis is “Dead” (1991 – 2005) A. Richard Newton, “Has CAD for VLSI reached a dead end?” VLSI ’91 A. Richard Newton, “Has CAD for VLSI reached a dead end?” VLSI ’ K. Keutzer, A. R. Newton, N. Shenoy, “The future of logic synthesis and physical design in deep- submicron process geometries”. ISPD ’97 K. Keutzer, A. R. Newton, N. Shenoy, “The future of logic synthesis and physical design in deep- submicron process geometries”. ISPD ’ R. Madhavan, “The death of logic synthesis”, Keynote at ISPD ’05 R. Madhavan, “The death of logic synthesis”, Keynote at ISPD ’05

5 Revival in Past 7 Years ABC AIG rewriting, priority cuts, resynthesis, sequential synthesis and verification, etc now SOPs, BDDs, ZDDs AIGs, BDDs AIGs, truth tables, SAT MVSIS Multi-valued network optimization, encoding, non-determinism, FSM synthesis, etc And-Inv Graphs (AIGs), tech-mapping, don’t- cares, equivalence checking, etc

6 ABC Highlights “Rewriting the book of logic synthesis” “Rewriting the book of logic synthesis” almost all classical methods have been replaced by fast heuristic iterative transforms almost all classical methods have been replaced by fast heuristic iterative transforms Based on methods that are Based on methods that are high speed high speed scalable scalable SAT-based SAT-based Becoming a new standard of reference for Becoming a new standard of reference for logic synthesis logic synthesis verification verification

7 Example of Emerging Logic Synthesis Equivalent AIG in ABC a b cdfe x yz Boolean network in SIS a b cd e xy f z AIG is a Boolean network of 2-input AND nodes and invertors (dotted lines)

8 One AIG Node – Many Cuts Combinational AIG a b cd f e Each node in an AIG has many cuts Each cut represents a different SIS node No a priori fixed boundaries Implies that AIG manipulation with cuts is equivalent to working on many Boolean networks at the same time Different cuts for the same node

9 Current Work (2007) ABC-5 Efficient combinational logic synthesis Fast, scalable, good quality Technology mapping with structural choices Cut-based, heuristic, good area/delay, flexible Sequential synthesis Innovative, efficient, scalable, verifiable Sequential verification Robust, integrated, interacts with synthesis

10 Next 5 Years ( ) Integrating synthesis/ mapping/retiming Larger space of solutions, improved quality ABC-8 Co-developing synthesis and verification Wider use of sequential transforms, improved quality Integrating synthesis with place and route Moving towards all-in-one solutions Improving AIG-based synthesis and mapping Faster, more scalable, better quality Creating configurable design flows Easy customization based on goals and resources Supporting emerging technologies Flexible solutions for the XXI century

11 Next 25 Years Is logic synthesis finally dead? Is logic synthesis finally dead? NO! NO! Alive and well and living in Berkeley? Alive and well and living in Berkeley? It is a fundamental issue It is a fundamental issue Difficult problems will force new solutions Difficult problems will force new solutions