FEE Electronics progress PCB layout 18th March 2009

Layout current 18th March 2009 Memory routing rules :- Data byte lanes and clocks routed to within 0.5mm Address and control bus routed using a tree structure with all branches equal in length Terminate data byte lanes both series and parallel. Terminate address and control bus to balance across all devices. Memory Target 400MHz data transfers 200MHz clocks

Layout to do 18th March 2009 Complete memory Gbit Ethernet. ADC output signals to the FPGA. Discriminator signal connections to the FPGA Mezzanine connector signal definition Clock distribution to the ADCs Power supply blocks and delivery planes. FPGA configuration memory. Temperature sensors, RS232, LEDs etc.

Problems Patrick on leave from April 3 rd to 20 th AGATA week in Cologne March 30 th to April 1 st. Pcb data needed at manufacturers by 9 th March Revised bill of materials (BOM) needed by assembler as soon as possible. Too many interruptions ! 18th March 2009