Phase 2 Tracker Meeting 6/19/2014 Ron Lipton Updates: First PS support mechanics meeting last week: Begin to import CERN design files Start to look at cooling optimization for barrel R. Lipton

Bump Bond Studies Sensor wafers complete ROIC wafers at Cornell, UCD Needed 200 m^2 Wafer diameter 300 mm Wafer area 0.031415927 0.070685835 Fration utilized 0.7 number of wafers 9095 4042 Width 20 microns length 1627050 162.705 cm 32541000 Square microns thickness 1 micron area 0.0000002 cm^2 Al resistivity 2.65E-08 ohm-meter 2.65E-06 ohm cm resistor value 2.16E+03 Power watt 4.64E+01 volts Sensor wafers complete ROIC wafers at Cornell, UCD Heaters too resistive? Connection issue? R. Lipton

Ziptronix / licensed to Novati ‘Fermilab’ 3D-IC run Ziptronix / licensed to Novati Tezzaron / Novati Difference between Cu-Cu thermocompression and Cu DBI wafer bonding methods: Cu-Cu not reworkable, bonding established by fusing metal pads, forgiving on surface planarity Cu DBI reworkable shortly after bonding, bonding established by chemically fusing oxide surfaces, must be ultra planar 3 CMS review, March 18-19, 2013

3D Process Development The original cu-cu bonding technique developed by Tezzaron had several issues Aging of top copper Wafer misalignment (Too) Aggressive design rules - 2.7 mm octagons on a 4 mm pitch alignment between wafers must be better than 1 um The DBI-oxide bonding process solved these problems. Misaligned Bond Interface in Cu-Cu bonded wafer L M R L M R Cu-Cu DBI Alignment Keys R. Lipton

Interconnect array Ziptronix DBI bonding array Bump bond pad 6 micron thick top silicon 4 micron pitch DBI Copper pillars

Sensor Integration – Three tier devices We then chip-to-wafer oxide bonded 3D chips to BNL sensors to form integrated sensor/electronics assemblies – parts received in March This completes our initial 3D work with Tezzaron and Ziptronix VIP(ILC), VICTR(CMS), and VIPIC(X-Ray) assemblies VIP VICTR VIP VIPIC VIPIC R. Lipton R. Lipton

Chip-to-Wafer bond DBI bonding of ROICs (VICTR, VIPIC, VIP) to BNL sensor wafer R. Lipton

Wafer with bonded Chips R. Lipton

VIP 2-tier VIP chip 24 micron pitch pixels 192x192 34 m sensor R. Lipton

DBI Interconnect VIPIC pixel Interconnect structure Shield metal Pad redistribution Alignment structures R. Lipton

Mounted detectors .5 mm sensor 34 micron 2-tier VICTR chip R. Lipton

3D-IC: Fermilab designs – VIPIC 1400 transistors / pixel 280 transistors / pixel Digital part of pixel Analog part of pixel 64 × 64 array of 80 mm2; shaping time tp=250 ns, power ~25 mW / analog pixel, noise <<150 e- ENC Two dead-time-less modes of operation (64 × 64 matrix / in 16 sub-matrices of 4 × 64 pixels): timed readout of hits acquired at low occupancy (address and hit count) st=10ms imaging – counting of events Sparsified readout with priority encoder circuit (hit pixel address readout only) 12

VIPIC Sensor results Because we have both bump-bonded and oxide bonded VIPICs we can compare the performance directly R. Lipton

VIPIC Noise Noise = 38 e- Output noise on oxide bonded devices are close to pixels with no sensors bonded – low interconnect capacitance associated with oxide bond R. Lipton

VIPIC Gain Lower capacitance is also reflected by larger gain R. Lipton

VIPIC Sensor results R. Lipton

Other Results Just started testing VICTR Cd 109 Just started testing VICTR Initial threshold scan with Cd109 source Test Pulse noise ~700 e- (FEI4 front end designed for lower Cin) VIP not yet tested Open channel Test pulse R. Lipton