1 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 18: Wed 10/26/2011 (CoreGen Overview) Instructor: Dr. Phillip Jones Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA

2 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) MP3: Due 11/4 –IT should have resolved the issue that was causing problems running MP3 on some of the linux-X and research-X remote machines Weekly Project Updates due: Friday’s (midnight) Will post ML507 ucf for quick reference Announcements/Reminders

3 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) Project Grading Breakdown 50% Final Project Demo 30% Final Project Report –20% of your project report grade will come from your 5-6 project updates. Friday’s midnight 20% Final Project Presentation

4 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) FPL FPT FCCM FPGA DAC ICCAD Reconfig RTSS RTAS ISCA Projects Ideas: Relevant conferences Micro Super Computing HPCA IPDPS

5 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) Teams Formed and Topic: Mon 10/10 –Project idea in Power Point 3-5 slides Motivation (why is this interesting, useful) What will be the end result High-level picture of final product –Project team list: Name, Responsibility High-level Plan/Proposal: Fri 10/14 –Power Point 5-10 slides (presentation to class Wed 10/19) System block diagrams High-level algorithms (if any) Concerns –Implementation –Conceptual Related research papers (if any) Projects: Target Timeline

6 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) Work on projects: 10/ /9 –Weekly update reports More information on updates will be given Presentations: Finals week –Present / Demo what is done at this point –15-20 minutes (depends on number of projects) Final write up and Software/Hardware turned in: Day of final (TBD) Projects: Target Timeline

7 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) Initial Project Proposal Slides (5-10 slides) Project team list: Name, Responsibility (who is project leader) –Team size: 3-4 (5 case-by-case) Project idea Motivation (why is this interesting, useful) What will be the end result High-level picture of final product High-level Plan –Break project into mile stones Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip. –System block diagrams –High-level algorithms (if any) –Concerns Implementation Conceptual Research papers related to you project idea

8 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) Weekly Project Updates The current state of your project write up –Even in the early stages of the project you should be able to write a rough draft of the Introduction and Motivation section The current state of your Final Presentation –Your Initial Project proposal presentation (Due Wed 10/19). Should make for a starting point for you Final presentation What things are work & not working What roadblocks are you running into

9 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) Common Questions

10 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) Common Questions

11 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen A tool for generating/customizing components made available from Xilinx. A wide range of component families available –Basic FPGA components (Block RAM, multipliers) –More advanced components (Clock Managers) – Math cores –Communication protocol cores –Signal processing cores

12 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen BlockRAM DCM (Digital Clock Manger)

13 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen BlockRAM –18/36-Kbit size memory block distributed throughout the FPGA –Can be combined to create lager effective memory blocks –Important: See data sheet for the amount of memory resources available on a give FPGA DCM (Digital Clock Manger)

14 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) LUT Block RAM FPGA

15 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) Block RAM (36-Kbit) 10-bit Address_A 36-bit Data_in_A 36-bit Data_out_A 36-bit Address 1023 Address 0

16 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) Block RAM (36-Kbit) 12-bit Address_A 36-bit Data_in_A 36-bit Data_out_A 9-bit Address 4096 Address 0 Can configure to change size of each word

17 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) Block RAM (36-Kbit) 10-bit Address_A 72-bit Data_in_A 72-bit Data_out_A 72-bit Address 1023 Address 0 Can configure to change size of each word Block RAM (36-Kbit) Address 1023 Address 0

18 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) Block RAM (36-Kbit) 10-bit Address_A 36-bit Data_in_A 36-bit Data_out_A 36-bit Address 1023 Address 0 Can be 2-ported (dual-ported) 10-bit Address_B 36-bit Data_in_B 36-bit Data_out_B

19 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) Declare and Instantiate a core generated by coregen like any other component Example: RAM_1K_36bit -- Declare -- Instantiate

20 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM)

21 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM)

22 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) Target the 70FX FPGA (what we use for class)

23 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) Select type of core you want to build. In this case a RAM block Double-click

24 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) Set parameters Name

25 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) Set parameters Set size

26 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM)

27 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) Check Resources used Generate Core

28 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen BlockRAM DCM (Digital Clock Manger) –Takes an input clock an multiplies by a factor (M/D) M is the multiplier D is the divider –Can generate multiple clock –Can set phase relation between clock –Can be change dynamically at run-time (Advanced usage) –Also a Phase Locked-Loop version of the DCM exists

29 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (DCM) LUT Block RAM FPGA DCM

30 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) CoreGen (Block RAM) DCM M=? D=? CLK_in CLK_out_1x CLK_out_2x CLK_out_1x_180deg CLK_out_FX FX = M/D e.g. M= 8, D=2: then FX = 8/2 = 4 Lock Lock: Indicates when the output Clock of the DCM are stable and Read for use. reset <= reset_extern OR not(Lock)

31 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) Next Class Design Patterns and Compute Models –Chapter 5.1, Reading 7

32 - ECpE 583 (Reconfigurable Computing): CoreGen Overview Iowa State University (Ames) Questions/Comments/Concerns Write down –Main point of lecture –One thing that’s still not quite clear –If everything is clear, then give an example of how to apply something from lecture OR