Ulrich Abelein, Mathias Born, Markus Schindler, Andreas Assmuth, Peter Iskra, Torsten Sulima, Ignaz Eisele Doping Profile Dependence of the Vertical Impact Ionization MOSFET’s (I-MOS) Performance Nano and Giga Challenges in Electronics and Photonics NGC 2007 Phoenix, Arizona, USA 16 March 2007

NGC 2007 Ulrich Abelein1 Overview Motivation Vertical Impact Ionisation MOSFET (IMOS): –Device Concept –Influence of Doping Profiles Electrical Characterization Summary and Outlook

NGC 2007 Ulrich Abelein2 Motivation Conventional MOSFET: Subthreshold slope S = dV G /d(logI D ) is diffusion limited.  min S = kT/q · ln10 = K Minimum static leakage current I LEAK : I LEAK = I D (V T ) · 10 -V T /S Shrinking the feature size according to Moore‘s Law makes a reduction of V T necessary.  I LEAK  Solution  Reducing S below the kT/q limit!  Achievable by gate controlled impact ionisation  Impact Ionisation MOSFET (IMOS)

NGC 2007 Ulrich Abelein3 Device Concept – Device Structure n+ Si source n+ Si drain i- Si p+ delta layer Gate oxide (4.5 nm) Gate oxide (4.5 nm) Drain contact n+ Poly Gate contact Source contact Spacer Schematic drawing of the vertical IMOS (above) and SIMS profile of the mesa layer stack (left hand side)

NGC 2007 Ulrich Abelein4 Device Concept – Simulation Results n+ Si source n+ Si drain i- Si p+ delta layer Gate oxide Drain contact n+ Poly Gate contact Source contact Spacer Energy in eV Ionisation rate in pairs / (cm 3  s) 0 80 Distance in nm Drain Source V GS =V DS =0 V V GS =0 V; V DS =2 V V GS = V DS =2 V  p+ delta barrier lowered by gate field  High field between p+ delta layer and drain causes impact ionisation Simulations of the electric field and the ionisation rate in the channel region

NGC 2007 Ulrich Abelein5 Device Concept – Operating Modes V DS < 1.25 V  Conventional MOSFET mode 2.2 V > V DS > 1.25 V  Impact Ionization Mode  Holes generated by impact ionization charge the body. Dynamic lowering of V T ! V DS > 2.2 V  Bipolar Mode  Parasitic bipolar transistor contributes to I D W = 2µm

NGC 2007 Ulrich Abelein6 Device Concept – Operating Modes V DS < 1.25 V  Conventional MOSFET mode V DS > 1.25 V  Beginning of significant impact ionziation  Holes generated by impact ionization charge the body  Dynamic lowering of V T  S is reduced below kT/q W = 2 µm

NGC 2007 Ulrich Abelein7 Influence of Doping Profiles Unintentional changes in doping profiles due to diffusion!  p+ delta layer doping diffuses into intrinsic zones! Diffusion   Sharper delta layer, larger barrier, higher eelctric fields!  Impact Ionization rates  (at const. V DS )  Lower S due to increased body charge for low V DS Diffusion   Lower barrier  Switch on voltage of parasitic bipolar transistor   Extremley low S due to current amplification  Hysteresis in input characteristics

NGC 2007 Ulrich Abelein8 Experimental Results – Doping Profiles Using 750 °C and 800 °C gate oxide process: Decreasing of boron diffusion for 750 °C  Maximum doping level increased by a factor of 3  Larger barrier!

NGC 2007 Ulrich Abelein9 Electrical Characerization – Output Characteristics Low thermal budget sample  Impact ionization mode begins at lower voltage  Later transistion to bipolar mode  V DS = 2.25 V LT sample in Impact Ioniziation mode HT sample in bipolar mode W = 2 µm

NGC 2007 Ulrich Abelein10 Electrical Characerization – Input Characteristics V DS = 2.25 V  LT sample in Impact Ioniziation mode  S = 4 mV/dec  No hysteresis! W = 2 µm

NGC 2007 Ulrich Abelein11 Electrical Characerization – Input Characteristics V DS = 2.25 V  HT sample in bipolar mode  S = 1.06 mV/dec!  Hysteresis visible  Gate controlled switch-off possible! W = 2µm

NGC 2007 Ulrich Abelein12 Summary and Outlook Summary: Influence of boron diffusion on device performance was shown Subthreshold slope of 1.06 mV/dec was shown Devcie can be optimized to needs of application –Very low subthreshold slope with measurable hysteresis –Low subthreshold slope without any hystersis Outlook: Realization of the p-channel device Shrinking device dimensions and reducing supply voltages