Low-Power, Low-Phase Noise SiGe HBT Static Frequency Divider Topologies up to 100 GHz Ekaterina Laskin, Sean T. Nicolson, Sorin P. Voinigescu University of Toronto, Canada Pascal Chevalier, Alain Chantre, Bernard Sautreuil, STMicroelectronics, France

Outline Motivation Static divider topology Fabrication technologies Test setup and results Conclusion 10 October 2006 Paper Number 12.3

Motivation Applications at 80 GHz: Phase-locked loop Radio circuits Comparison of divider topologies Technology benchmark 10 October 2006 Paper Number 12.3

Static Divider Topology On-chip transformer and matching Toggle flip-flop, 50 Ω output buffer 2 different latch designs implemented 10 October 2006 Paper Number 12.3

Integrated Transformer primary 30µm secondary Stacked design, top 2 metals over substrate 30µm square, 1µm spacing, 2µm metal width 10 October 2006 Paper Number 12.3

Transformer Model primary k secondary substrate model Model extracted from geometry using ASITIC π - network includes substrate model k = 0.855 is achieved 10 October 2006 Paper Number 12.3

Input Network Simulation Divider input matched 40 – 100 GHz Transformer operational up to 100 GHz 10 October 2006 Paper Number 12.3

Latch Design 1 – w/o input EF ECL latch Inductive peaking No split load Self-biased Resistive input biasing 10 October 2006 Paper Number 12.3

Latch Design 2 – with input EF Double-EF input buffer 10 October 2006 Paper Number 12.3

Implementation Both dividers fabricated in 2 SiGe processes: BiCMOS9 0.1 1 10 50 100 150 200 250 300 J C (mA/ m 2 ) f T MAX 0.1 1 10 50 100 150 200 250 300 J C (mA/ m 2 ) f T MAX BiCMOS9 BipX 10 October 2006 Paper Number 12.3

Fabricated Dividers with input EF w/out input EF BiCMOS9 BipX 10 October 2006 Paper Number 12.3

Fabricated Dividers with input EF w/out input EF BiCMOS9 BipX 10 October 2006 Paper Number 12.3

Fabricated Dividers with input EF w/out input EF BiCMOS9 BipX 10 October 2006 Paper Number 12.3

Fabricated Dividers with input EF w/out input EF BiCMOS9 BipX 10 October 2006 Paper Number 12.3

Fabricated Dividers with input EF w/out input EF BiCMOS9 BipX 515μm × 473μm 3.3 V 145 mW 502μm × 360μm 3.3 V 122 mW 10 October 2006 Paper Number 12.3

Test Setup 0 - 50 GHz: 50 - 75 GHz: 75 - 100 GHz: 10 October 2006 Paper Number 12.3

Measurement Results Divider self-oscillation frequency: BipX1 BipX2 40 45 50 55 60 65 70 75 80 220 240 260 280 300 Process f MAX (GHz) Divider SOF (GHz) Divider with EF Divider w/out EF BipX BiCMOS9 BipX1 BipX2 10 October 2006 Paper Number 12.3

Sensitivity Curves 25 °C BipX, w/o EF BipX, w/ EF BiCMOS9, w/o EF -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 Input Frequency [GHz] Input Power [dBm] BipX, w/o EF BipX, w/ EF BiCMOS9, w/o EF BiCMOS9, w/ EF 25 °C 10 October 2006 Paper Number 12.3

Sensitivity Curves 25 °C 50 °C 100 °C Input Power [dBm] -50 -40 -30 -20 -10 10 20 30 40 50 60 70 80 90 100 Input Frequency [GHz] Input Power [dBm] 25 °C 50 °C 100 °C 10 October 2006 Paper Number 12.3

Divider Phase Noise Input Output 100 GHz -90.4 dBc/Hz @ 100 kHz offset Phase noise -6 dB with frequency halving 10 October 2006 Paper Number 12.3

Further Improvements MOS-HBT HBT only BiCMOS9, HBT only 20 -50 -40 -30 MOS-HBT 10 -10 Input Power [dBm] HBT only -20 BiCMOS9, HBT only BiCMOS9, MOS-HBT BipX, HBT only 10 20 30 40 50 60 70 80 90 100 Input Frequency [GHz] 10 October 2006 Paper Number 12.3

Comparison to Previous Work [6] [5] [9] [7] [8] [2] This Work 30 40 50 60 70 80 90 100 200 300 400 500 Technology fT [GHz] Divider SOF [GHz] InP CMOS SiGe 10 October 2006 Paper Number 12.3

Conclusion 2 SiGe static dividers designed and analyzed in 2 technologies Designed divider operates up to 100 GHz Features an integrated transformer operating at 100 GHz Ideal phase noise behaviour Low power 10 October 2006 Paper Number 12.3

Thank You 10 October 2006 Paper Number 12.3

Back-up Slides 10 October 2006 Paper Number 12.3

50-Ω Output Buffer 10 October 2006 Paper Number 12.3

BipX Process Splits BipX2 BipX1 I (mA) f I (mA) f 0.1 1 10 50 100 150 50 100 150 200 250 300 I C (mA) f MAX T 0.1 1 10 50 100 150 200 250 300 I C (mA) f MAX T BipX2 BipX1 10 October 2006 Paper Number 12.3

Measurement Results Divider self-oscillation frequency: BiCMOS9 BipX 40 45 50 55 60 65 70 75 80 170 190 210 230 250 270 Process f T (GHz) Divider SOF (GHz) Divider with EF Divider w/out EF BiCMOS9 BipX BipX2 BipX1 10 October 2006 Paper Number 12.3

Measurement Results with input EF w/out input EF BiCMOS9 avg= 45.9 GHz s.dev.= 1.54 GHz BipX avg= 65.02 GHz avg= 72.43 GHz s.dev.= 2.06 GHz 10 October 2006 Paper Number 12.3

Source Phase Noise @ 100GHz 10 October 2006 Paper Number 12.3

BiCMOS Divider 10 October 2006 Paper Number 12.3