Advanced SW/HW Optimization Techniques for Application Specific MCSoC m Yumiko Kimezawa Supervised by Prof. Ben Abderazek Graduate School of Computer Science and Engineering Adapted Systems Laboratory August 24, 2011Master's Thesis Research Plan1

Outline 1.Background 2.Problems 3.Research goal 4.Research approach 5.Research Schedule August 24, 2011Master's Thesis Research Plan2

Background Electrocardiography (ECG) -Electrical activity of the heart -Used for diagnosis of heart disease Processing ECG signals involves heavy computation Previous proposed ECG processing system -Parallel processing using additional cores for analyzing ECG signals August 24, 2011Master's Thesis Research Plan3

Background Period-Peaks Detection (PPD) Algorithm (1) Figure: A typical ECG graph August 24, 20114Master's Thesis Research Plan

Period detection Peaks processing Data reading Derivation Autocorrelation Finding interval Extraction Store of results Discrimination August 24, 20115Master's Thesis Research Plan Background Period-Peaks Detection (PPD) Algorithm (2) A. Ben Abdallah, Y. Haga, K. Kuroda, An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records, IEEE Proc. of the 39th he International Conference on Parallel Processing, San Diego, pp , Sept , 2010.An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records

The system consists of mainly 2 modules Master module -Signal reading, filtering and display part PPD module -Analyzing ECG signal using Period-Peaks Detection (PPD) algorithm August 22, 20116Master's Thesis Research PlanAugust 24, 20116Master's Thesis Research Plan Background System Base Architecture (1)

3-lead system is implemented -The total logic utilization is about 3 times as large as one of single-lead system - The total processing time is about 50 % from the single lead system ADC 1 ADC 12 FIR 1 FIR12 Buffer ECG Signal Analysis 1:Signal reading 2:Filtering3:Analysis4:Display 12 leads External Memory Patient: A P = # mV Q = # mV R = # mV S = # mV T = # mV U = # mV Interval = # ms Not implemented Our ideal system architecture August 24, Master's Thesis Research Plan Background System Base Architecture* (2) * A. Ben Abdallah, Y. Haga, K. Kuroda, An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records, IEEE Proc. of the 39th he International Conference on Parallel Processing, San Diego, pp , Sept , 2010.An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records

Problems BANSMOM runs sample data only -Can not read actual data -Difficultly estimation of real processing time -Cannot estimate real system complexity and power Low hardware usability -The more leads, the more larger logic utilization Current driver software is not parallelized well August 24, 20118Master's Thesis Research Plan

Research Goal Research about software and hardware optimization techniques for Embedded Multicore SoC (BANSMOM) -Capturing and analyzing of real ECG signals -Research about HW optimization -Parallelizing PPD algorithm (driver software) August 24, 20119Master's Thesis Research Plan

Research Approach (1) Hardware/Software optimization -Hardware Adding A/D converters Fast data transfer between each memory DMA controller -Software Parallelizing Period-Peaks Detection (PPD) algorithm by refining the code and looking for parallel tasks August 24, 2011Master's Thesis Research Plan10

11 Period detection Peaks detection Reading data Derivation Autocorrelation Find interval Extraction of max point Store results Discrimination Master's Thesis Research Plan Based on autocorrelation approach Research Approach (2) Parallelizing this phase August 24, 2011

Research Approach (3) : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU External Memory External Memory Shared Memory Shared Memory FPGA Analog ECG data from the sensor Line-in Data conversion HSMC A/D converter DMA controller August 24, Master's Thesis Research Plan

Evaluation methodology Environment -Language: Verilog HDL -Tools: Quartus II, SOPC Builder, and NIOS II IDE -Target device: Stratix III DSP Board (EP3SL150F1152C2) -Target data: actual ECG signals Parameters -Hardware complexity -Processing time February 9, GT2010

August 24, Master's Thesis Research Plan Investigating suitable resolution and sampling rate for A/D conversion Selecting appropriate an A/D converter Adding the A/D converter into the system Getting actual data using the sensor Adding DMA controller into the system Optimization of software Verification of the system Writing master’s thesis Research Schedule

Thank you for listening August 24, Master's Thesis Research Plan