1 Quarterly Technical Report II for Pittsburgh Digital Greenhouse Kyusun Choi The Pennsylvania State University Computer Science and Engineering Department High Speed CMOS A/D Converter Circuit for Radio Frequency Signal

2 Summary of the Quarterly Report II(1) Project goals for this quarter 1.First prototype chip test 2.Test report 3.Design second prototype chip: 6bit and 8bit design in 0.18  m

3 Summary of the Quarterly Report II(2) Accomplished project milestones 1.Total 25 prototype chips are received 6 ADCs are in each prototype chip -6bit high speed ADC -6bit low power ADC -8bit high speed ADC -8bit low power ADC -9bit high speed ADC -9bit low power ADC

4 Summary of the Quarterly Report II(3) Accomplished project milestones 2. All 25 prototype chips are working 3. Initial test results for six ADCs : ADCsPrecisionADC signal delay 6bit high speed4 bits3.799 ns 6bit low power6 bits ns 8bit high speed5 bits7.249 ns 8bit low power7 bits ns 9bit high speed6 bits ns 9bit low power8 bits ns

5 Summary of the Quarterly Report II(4) Accomplished project milestones LSB’s Delta-W (from layout design) ADCs  LSB (mV)  W hp (  m)  W hn (  m)  W mp (  m)  W mn (  m)  W lp (  m)  W ln (  m) 6bit high speed bit low power bit high speed bit low power bit high speed bit low power

6 Summary of the Quarterly Report II(5) Accomplished project milestones 4. Chip testing and parameter extraction 5. Second prototype chip design in 0.18  m technology (on going) Tape-out target date: 8/5/2001 Vendor: MOSIS with TSMC 0.18 um foundry Expected prototype chip delivery date: 10/25/2001

7 Summary of the Quarterly Report II(6) Publications Paper Published in WVLSI “ A 1-GSPS CMOS Flash Analog-to-Digital Converter for System-on-Chip Applications” (April 2001) Paper Accepted in ASIC/SOC “ Future-Ready Ultrafast 8bit CMOS ADC for System-on– Chip Applications” (September 2001)

8 Prototype Chip(1) Prototype chip photo

9 Prototype Chip(2) Chip die photo

10 Prototype Chip(3) Chip die corner photo

11 Prototype Chip(4) Output pad driver photo

12 Prototype Chip(5) Prototype chip tester setup

13 Chip Test Results(1) ADC Operation with 6bit low power ADC 100 KHz triangle wave

14 Chip Test Results(2) ADC Operation with 6bit low power ADC 400 KHz sine wave

15 Chip Test Results(3) ADC Operation with 6bit low power ADC 1 MHz square wave

16 Chip Test Results(4) Delay of pad and multiplexor Pad and multiplexor circuit

17 Chip Test Results(5) Delay of pad and multiplexor Actual measurement (Tin to Tout)

18 Chip Test Results(6) Delay of pad and multiplexor Actual measurement (Tin to Tout) Simulation results ADCsR. delayF. delayAvg. delay Chip # ns2.850 ns3.150 ns Chip # ns2.825 ns3.150 ns Chip # ns2.875 ns3.563 ns ProcessesMux delayPad + Mux delay T14Y_LO_EPI0.414 ns1.144 ns TSMC_TT0.332 ns0.864 ns

19 Chip Test Results(7) ADC signal operation Block diagram

20 Chip Test Results(8) ADC signal operation (0 V to 2.5 V) Actual measurement (nSec) ADCsChip #6 Chip #15 Chip #16 6bit high speed bit low power bit high speed bit low power bit high speed bit low power

21 Chip Test Results(9) ADC signal operation (0 V to 2.5 V) Simulation with T14Y_LO_EPI (nSec) ADCst_compt_gb1t_gb2t_gent_romt_out 6bit high speed bit low power bit high speed bit low power bit high speed bit low power

22 Chip Test Results(10) ADC signal operation (0 V to 2.5 V) Simulation with TSMC_TT (nSec) ADCst_compt_gb1t_gb2t_gent_romt_out 6bit high speed bit low power bit high speed bit low power bit high speed bit low power

23 Chip Test Results(11) ADC signal operation (0.6 V to 1.7 V) Actual measurement (nSec) ADCsChip #6Chip #15Chip #16 6bit high speed bit low power bit high speed bit low power bit high speed bit low power

24 Chip Test Results(12) ADC signal operation (0.5 V to 1.76 V) Simulation with T14Y_LO_EPI (nSec) ADCst_compt_gb1t_gb2t_gent_romt_out 6bit high speed bit low power bit high speed bit low power bit high speed bit low power

25 Chip Test Results(13) ADC signal operation (0.5 V to 1.76 V) Simulation with TSMC_TT (nSec) ADCst_compt_gb1t_gb2t_gent_romt_out 6bit high speed bit low power bit high speed bit low power bit high speed bit low power

26 Chip Test Results(14) DNL and INL measurement DNL with 6bit low power ADC - Chip #12 ChipDNL #60.49 #120.27

27 Chip Test Results(15) DNL and INL measurement INL with 6bit low power ADC - Chip #12 ChipINL #61.19 #121.20

28 Chip Test Results(16) DNL and INL measurement Simulation results (LSB) ADCsT14Y_LO_EPITSMC_TT DNLINLDNLINL 6bit high speed bit low power bit high speed bit low power bit high speed bit low power

29 Chip Test Results(17) Power consumption Actual measurement (mWatt) ADCsSampling rate (msps) Avg. Power Max. Power 6bit high speedcontinuous109.38N/A 6bit low powercontinuous35.25N/A 8bit high speedcontinuous170.50N/A 8bit low powercontinuous121.25N/A 9bit high speedcontinuous N/A 9bit low powercontinuous N/A

30 Chip Test Results(18) Power consumption Simulation results (mWatt) ADCsSampling rate (msps) T14Y_LO_EPITSMC_TT Avg.Max.Avg.Max. 6bit high speed bit low power bit high speed bit low power bit high speed bit low power

31 Chip Test Results(19) Noise Power supply noise

32 Chip Test Results(20) Noise Noise on ADC input pin

33 Chip Test Results(21) Noise Effects of noise to ADC output

34 Test Evaluation(1) All 25 prototype chips are working 1.Best working : 6bit low power ADC Full 6bit precision without missing code 2.Better working : 9bit low power ADC 7bit operation without missing code 8bit operation with few missing code 3.Other ADCs Working but with lower precision High speed ADC outputs show more noise and less precision

35 Test Evaluation(2) Signal delay 1. ADC design and simulation TSMC_TT parameters 2.The wafer test result T14Y_LO_EPI parameters Re-simulation with T14Y_LO_EPI : 10% - 30% more signal delays 3.The actual measurements at least 50% longer signal delays Some possible reasons

36 Test Evaluation(3) Reduced precision 1.Process limitation Layout dimension LSB’s  W 2.On-chip power distribution Separating analog power line 3.Noise on ADC input High frequency noise appear on the ADC input High frequency noise from power supply line

37 Test Evaluation(4) Others 1.Power consumption Good match with simulation results Overall 10-20% less than simulation 2.INL and DNL INL and DNL are significantly increased INL increase > 1.0 bit LSB DNL increase < 0.4 bit LSB 3.Process variation on same wafer Less than 3% variation Overall consistent among the chips

38 Test Evaluation(5) Future testing to be done 1.DC specification test Temperature drift effect Power supply variation 2.AC specification test & characterization Signal-to-noise and distortion ratio Effective number of bits Signal-to-noise ratio Total harmonic distortion Spurious free dynamic range Other dynamic performance

39 Second Prototype Chip Design(1)  m CMOS technology 6bit, 8bit, and 9bit ADCs Better precision 2. New pad frame design 3 sets of separate on-chip power supply distribution system 84 pin package 3. Limit LSB’s Delta-W  W = 0.1  m or 0.05  m

40 Second Prototype Chip Design(2) 4. Sample and hold + 2 stage pipeline Adding sample and hold circuit Adding digital pipeline registers 5. Single inverter comparator Test ADC with single inverter comparator Determine high frequency operation limits 6. ADC input shielding Provide analog input shielding on chip

41 Conclusion 1. Mission success for the first prototype chip fabrication 6bit TIQ based ADC Limits of TIQ based ADC 2. Major mistakes on the first prototype chip design 3. Expectation of second prototype chip Full precision 6bit and 8bit ADCs on-chip