CBP 2005Comp 3070 Computer Architecture1 Last Time … All instructions the same length We learned to program MIPS And a bit about Intel’s x86 Instructions of variable length

CBP 2005Comp 3070 Computer Architecture2 Today the consequences of … Intel (CISC) MIPS (RISC)

CBP 2005Comp 3070 Computer Architecture3 Laundry Model Washer Drier Store Basket Wardrobe

CBP 2005Comp 3070 Computer Architecture4 Process Steps A. Wash then Dry idle running time Load the washer at Done at 10, load the drier 3.Drier Done at 11

CBP 2005Comp 3070 Computer Architecture5 Sequential Process 3 loads takes 6 hours time Load washer at Done at 10, load drier 3.Drier Done at 11 4.Reload washer at 11 5.Done at 12, load drier 6.Drier done at 13 7.Reload washer at 13 8.Done at 14, load drier 9.Done at

CBP 2005Comp 3070 Computer Architecture6 Overlapping Process 3 loads takes 4 hours time Load washer at Done at 10, load drier reload washer 3.Both Done at 11. Reload drier reload washer 4.Both done at 12. Reload drier 5.Drier done at From till both washer and dryer running concurrently

CBP 2005Comp 3070 Computer Architecture7 Washing Pipeline Filling time loads in 9 hours 5 Cycles !!! 1.Get washing 2.Wash 3.Dry 4.Store 5.Put away

CBP 2005Comp 3070 Computer Architecture8 Washing Pipeline Full time Pipe Full gives 1 load per hour

CBP 2005Comp 3070 Computer Architecture9 Pipelining : Comments time Potential speedup = number of stages Time to ‘fill’ and ‘drain’ reduces speedup Rate limited by slowest step

CBP 2005Comp 3070 Computer Architecture10 Can we Pipeline SAM ? Data Memory Instruction reg Code Memory ALU r1 r2 r0 X Y W XY W mar mdr 1.Fetch 2.Dec/ Reg 3.ALU 4.Mem 5.RW

CBP 2005Comp 3070 Computer Architecture11 Pipelined Sam4 Data Memory X Y W Y W r1 r2 r0 X Code Memory 1.Fetch2.Dec/ Reg 3.ALU4.Mem5.RW Buffer time

CBP 2005Comp 3070 Computer Architecture12 5 Stages in Pipeline ALU Mem Reg MemReg add r3,r1,r2 r1,r2 r3 add Let’s take the instruction add r3,r1,r2 and show which stage is needed for each part of the instruction. 1.Fetch 2.Dec/ Reg 3.ALU4.Mem5.RW time

CBP 2005Comp 3070 Computer Architecture13 ld r0 Memr3 Two Instructions ld r3,[r0+2] Two instructions into the pipeline add r4,r1,r2 ALU add r1,r2 r4 r0 2 time

CBP 2005Comp 3070 Computer Architecture14 Structural Hazard ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg Here we are being asked to read from memory and write to it simultaneously. Impossible! Write (store) Read (fetch) Solution – Use separate code and data memories add r4,r1,r2 st r0,[5]

CBP 2005Comp 3070 Computer Architecture15 Hazardous Washing time Washing basket containes both clean and dirty washing!

CBP 2005Comp 3070 Computer Architecture16 Code and Data Memories ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg

CBP 2005Comp 3070 Computer Architecture17 add r1,r2 r3 Data Hazard add r3,r1,r2 but need r3 here EARLIER ! add r4,r1,r3 add r1,r3 r4 r3 set here time

CBP 2005Comp 3070 Computer Architecture18 Data Hazard ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg add r3,r1,r2 add r4,r1,r3 Need value of r3 for second instruction before the first is complete.

CBP 2005Comp 3070 Computer Architecture19 Pipeline Stalls ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg Mem ALU Reg MemReg Stall ALU Mem Reg MemReg add r3,r1,r2 add r4,r1,r3 Resolve Hazard – Insert delay into second instruction stream. ‘Stall’ Cycles. But this needs extra electronics on the chip. Complex and Costly.

CBP 2005Comp 3070 Computer Architecture20 Forwarding ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg add r3,r1,r2 add r4,r1,r3 Need value of r3 for second instruction before the first is complete. So build in extra circuits to get the data as soon as it is available from the ALU

CBP 2005Comp 3070 Computer Architecture21 Compiler resolves Hazard ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg ALU Mem Reg MemReg add r3,r1,r2 add r4,r1,r3 Compile can detect possible hazard and insert 2 nops (‘no ops’) ALU Mem Reg MemReg ALU Mem Reg MemReg nop

CBP 2005Comp 3070 Computer Architecture22 Example op code regs alu mem reg write ld r1,[7] ld r2,[8] add r3,r1,r2 ld r1 [7] ld r2 [8] add r1, r2 r3

CBP 2005Comp 3070 Computer Architecture23 Exercise op code regs alu mem reg write ld r1,[7] add r1,r2,r0 add r3,r1,r2

CBP 2005Comp 3070 Computer Architecture24 Control (branch) Hazard ? beq r1,r2 Test done add r1,r2 r3 st r3 [64] st r2 [68] ld 124 [124]r1 4 beq r1,r2,20 8 add r3,r1,r2 12 st r3,[64] 16 st r2,[68] 20 ld r1,[124] Program may branch to 20 If r1 = r2 branch to 20 Test if r1 = r2 done by ALU. Result known only in stage 4 Run from here now Must FLUSH these

CBP 2005Comp 3070 Computer Architecture25 Branch Hazard Resolution Let’s just assume the branch will NOT be taken So the following instruction needs to be executed And this is already in the pipeline So we make no changes to our CPU hardware design We will be wrong 50% of the time, at a guess. Then we have to flush the pipeline The above assumption is a crude form of Branch Prediction Could keep a branch prediction table storing the results of previous branches. Use this to make a statistics based decision