Custom Computing Machines for the Set Covering Problem Paper Written By: Christian Plessl and Marco Platzner Swiss Federal Institute of Technology, 2002 Presentation By Greg Jackson 1

Overview Introduction to the Problem Current Solutions Proposed Reconfigurable Architecture Implementation Experimentation Results 2

The Problem Boolean Satisfiability (SAT) ◦ A discrete decision problem whereby variables are found such that a boolean expression in Conjunctive Normal Form(CNF) is evaluated true. CNF? ◦ Given Expression – (A and B) or C ◦ CNF Equivalent – (A or C) and (A or B) 3

The Problem The Set Covering Problem is a Minimum Cost SAT Problem “Given a set U of elements and a set S of subsets ti of U, i = 1... |S|, find the smallest subset T, that contains all elements of U” 4

The Problem Often in Expressed in Matrix Form The Matrix A is a subset of columns with at least one entry for all the variables (A, B, C, D) 5

The Problem The Set Covering problem is often associated with the Synthesis of Reconfigurable Designs Logic Optimization that occurs during synthesis is a Set Covering Problem ◦ e.g. Two-level logic minimization, state minimization 6

Current Solutions Software - Mini & Espresso ◦ Utilizes a technique called Branch and Bound ◦ Heuristic Methods  Variable Order, Order of Value Assignments etc. Branch and Bound ◦ The software creates search trees and iterates over all values, trimming the trees as possible solutions are ruled out 7

Branch and Bound A – Matrix Defining the Set Covering Problem V – Current Variable Assignment B – Current Low Cost Solution Heuristics can be applied to Algorithm ◦ Variable Order ◦ Value Assignments Algorithm can be Bounded by Cost 8

Why Did They Do It? Faster ◦ Speedups in the order of several magnitudes to solve more problems Evaluation of Heuristics ◦ Need fast solvers to evaluate the performance of heuristics and approximations Development of New Heuristics ◦ New methods = New Heuristics 9

Proposed Architecture Basic Accelerator - Four Blocks ◦ An Array of finite state machines (FSMs) ◦ Checker Modules ◦ Cost Counter ◦ Controller Architecture utilizes 3-valued Logic ◦ {1,0,X} 10

Proposed Architecture FSM ◦ Implementation of the Branch and Bound in Hardware 11

Search Heuristics Two Things Affecting Efficiency ◦ Variable Order  Index Order – Variables are placed in order of their index  Frequency Order – Variables that appear frequently are placed at the top of the array ◦ Assignment Order  0 – 1 – FSM assigns a 0 first to the CNF  1 – 0 – FSM assigns a 1 first to the CNF  Random 12

Cost Bound Limit on the amount of assignments This limits the length of the search 13

Hardware Reductions 3 Ways ◦ Don’s Cares ◦ Essentials ◦ Dominated Columns This Creates a New State Machine 14

Implementation Implemented 4 Architectures ◦ CE – Basic ◦ CEDC – Don’t Cares ◦ CEDCES – Essentials ◦ CEDCESDCOL – All 3 forms of Hardware reduction Used Xilinx Virtex XCV1000 and simulated the system using ModelSim 15

Experiments Used two sources for test problems ◦ Two-level logic minimization ◦ Steiner triple system Selected 21 problems from Espresso distribution for testing Test Problems Have 4-62 Variables and 4-70 clauses (i.e. A or B) Would then compare the accelerator to the software implementation 16

Results – Raw Speedup Compared the runtimes to that of the Software Did not take into account delays i.e. Code generation, synthesis, etc. Using the CEDCESDCOL accelerator, achieved orders of magnitude speed up Average Speedup – 4 orders of magnitude over the Software 17

Results – Relative Speedup Compared the architectures to each other in terms of speed up For the graph, used best performance heuristics The CEDCESDCOL architecture was the fastest 18

Results – Heuristic Performance Used the four different architectures and determined which heuristics worked best for each Example: CEDCES ◦ Variable Order – Frequency Variable Order ◦ Variable Assignment – Random 19

Conclusions Speedups were promising but... ◦ The tested problems were too small and can be solved in seconds in software (5ms – 1.3s) ◦ The synthesis time of the designs were in the order of minutes ◦ Reducing the hardware made the accelerators slower with larger problems when compared to the software. Suggest a Hardware/Software Accelerator ◦ Speed up of Hardware + Sophistication of Software 20

Final Thoughts Extensive Paper It was a Continuation of a Previous Paper Useful application Hardware Reductions not Explained Well 21