Kandemir224/MAPLD Reliability-Aware OS Support for FPGA-Based Systems M. Kandemir, G. Chen, and F. Li Department of Computer Science & Engineering The Pennsylvania State University, USA

Kandemir 224/MAPLD Introduction and Acronyms Increasing soft-error rates make reliability an important factor in system design Our focus: Reliability-aware OS scheduling for FGPA based systems FPGA: Field Programmable Gate Array CLB: Configurable Logic Block STG: SubTask Graph

Kandemir 224/MAPLD The Reconfigurable System CLB Configurable Logic Block a 6X8 CLB array the interconnects and input-output blocks are omitted Process 1 Process 2 Process 3

Kandemir 224/MAPLD Improving Reliability Traditionally, OS-scheduler schedules parallel executions of multiple processes to maximize FPGA space utilization Data dependencies between different processes might prevent the full utilization of FPGA space Our approach utilizes the available FPGA space to duplicate processes and improve reliability

Kandemir 224/MAPLD Duplicating Processes CLB Process 1 Process 2 Process 3 Duplicate of Process 3 Duplicate of Process 1

Kandemir 224/MAPLD Issues in Duplicating Processes Tasks (processes) have different criticality Each task may require a different amount of FPGA space Duplications can cause performance degradation We use a QoS parameter to indicate the maximum tolerable performance degradation A checker task is scheduled for each duplicated task to check the outputs of the primary task and the duplicate

Kandemir 224/MAPLD Subtask Graph (STG) ViVi VjVj Each process to be scheduled is presented by a subtask graph Each node represents a process code portion (subtask) that will be executed in a single quantum of time once it gets scheduled. The j th node of process i is denoted as STG ij Indicates a data or control dependence from v i to v j

Kandemir 224/MAPLD Subtask Graph ViVi VjVj Since our processes are extracted from the same application, there might be data dependences between different processes

Kandemir 224/MAPLD Our Approach Five Step Task duplication under QoS guarantees Current implementation focuses only on error detection Annotation step QoS specification step Task identification step Task ranking step Scheduling step

Kandemir 224/MAPLD Our Approach Annotation step QoS specification step Task identification step Task ranking step Scheduling step The application programmer indicates which data structure are critical from the reliability view point using annotations. The application programmer also indicates the tolerable latency during application execution as a result of the reliability provided.

Kandemir 224/MAPLD Our Approach Annotation step QoS specification step Task identification step Task ranking step Scheduling step An automatic application code analyzer analyzes the source code, and identifies tasks. Based on how these tasks operate on critical data, they are ranked. They are ordered from the most important task to the least important one.

Kandemir 224/MAPLD Our Approach Annotation step QoS specification step Task identification step Task ranking step Scheduling step The OS scheduler is modified such that whenever there is opportunity, the OS duplicates tasks that run on FPGA device. Whenever the scheduler predicts the QoS limit is about to be reached, it stops duplicating the tasks.

Kandemir 224/MAPLD Experimental Setup An error injection module injects errors with a specified probability Two real-life embedded applications: encr and usonic The performance of our reliability-aware scheduler is compared with that of a normal Short-Job-First scheduler Tolerate at most 5% performance degradation Rank tasks according to the frequency of accesses to critical data Fatal errors: Errors that would lead to crash of the application

Kandemir 224/MAPLD Experimental Data

Kandemir 224/MAPLD Ongoing Work Experimenting with a diverse set of benchmarks Implementing task duplication within other types of OS schedulers such as First-Come-First-Server

Kandemir 224/MAPLD Conclusion The OS scheduler tries to provide reliability through task duplication under QoS guarantees Improving FPGA space utilization by duplicating for reliability Providing reliability for critical tasks first Catching most fatal errors