Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 1 Raimund Ubar Tallinn Technical University D&T Laboratory Estonia Hierarchical Test Generation for Digital Systems REASON Days Minsk, Nov, 2004

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 2 Abstract How to improve the testing quality at increasing complexities of today's systems? Two main trends: defect-oriented test and high-level modelling –Both are caused by the increasing complexities of systems based on deep- submicron technologies The complexity problems in testing digital systems are handled by raising the abstraction levels from gate to register-transfer level (RTL) instruction set architecture (ISA) or behavioral levels To handle defects in circuits implemented in deep-submicron technologies, new fault models and defect-oriented test methods should be used Trends to high-level modelling and defect-orientation are opposite As a promising compromise and solution is: to combine hierarchical approach with defect orientation Decision Diagrams serve as a good tool for hierarchical modelling of defects in digital systems

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 3 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation Decision Diagrams - beyond BDDs Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation Overview of tools developed at D&T Lab

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 4 Introduction: Quality Policy Quality policy Yield (Y) P,n Defect level (DL) P a Design for testability Testing P - probability of a defect n - number of defects P a - probability of accepting a bad product - probability of producing a good product

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 5 Introduction: Defect Level DL T(%) YY Y(%) T(%) DL   T  Paradox: Testability   DL 

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 6 Introduction: the Problem is Money? Cost of testing Quality Cost of quality Cost Cost of the fault 100% 0% Optimum test / quality How to succeed? Try too hard! How to fail? Try too hard! (From American Wisdom) Conclusion: “The problem of testing can only be contained not solved” T.Williams Test coverage function Time 100%

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 7 Introduction Paradox 1: Digital world is finite, analog world is infinite. However, the complexity problem was introduced by Digital World Paradox 2: If I can show that the system works, then it should be not faulty. But, what does it mean: it works? 32-bit accumulator has 2 64 functions which all should work. So, you should test all the 2 64 functions ! All life is an experiment. The more experiments you make, the better (American Wisdom) System Stimuli Y Response X Y X Analog case (samples) Digital case (“continuous”)

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 8 Introduction: How Much to Test? Paradox: 2 64 input patterns (!) for 32-bit accumulator will be not enough. A short will change the circuit into sequential one, and you will need because of that 2 65 input patterns Paradox: Mathematicians counted that Intel 8080 needed for exhaustive testing 37 (!) years Manufacturer did it by 10 seconds Majority of functions will never activated during the lifetime of the system Time can be your best friend or your worst enemy (Ray Charles) & & x1x1 x2x2 x3x3 y State q Y = F(x 1, x 2, x 3,q) * 1 1 Y = F(x 1, x 2, x 3 ) Bridging fault 0

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 9 Two Approaches to Testing Testing of functions: 1 2 n Combinational circuit under test Truth table: Patterns 00…000 00…001 00…010 … 11…111 Functions … … …111 … …111 2n2n2n2n 1 1 2n2n2n2n 2 Number of patterns Number of functions 2 n 2 n-1 2 tested 50%! 0% Faulty functions covered by 1. pattern Faulty functions covered by 2. pattern 50% 75% 3. pattern 4. pat. 87,5% 93,75% 100%

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 10 Two Approaches to Testing Testing of structural faults: 1 2 n Combinational circuit under test Fault coverage 100% Number of patterns 4 4. pat. Not tested faults Faults covered by 1. pattern 2. pattern 3. patttern

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 11 Two Approaches to Testing Testing of functions: 100% will be reached only after 2 n test patterns Testing of faults: 100% will be reached when all faults from the fault list are covered 0% Faulty functions covered by 1. pattern Faulty functions covered by 2. pattern 50% 75% 3. pattern 4. pat. 87,5% 93,75% 100% Testing of faults Testing of functions 4. pat. Not tested faults Faults covered by 1. pattern 2. pattern 3. patttern

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 12 Introduction: Hierarchy Paradox: To generate a test for a block in a system, the computer needed 2 days and 2 nights An engineer did it by hand with 15 minutes So, why computers? The best place to start is with a good title. Then build a song around it. (Wisdom of country music) System 16 bit counter & 1 Sequence of 2 16 bits Sea of gates

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 13 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation Decision Diagrams (beyond BDDs) Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation Overview of tools developed at D&T Lab

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 14 Complexity vs. Quality Problems: Traditional low-level test generation and fault simulation methods and tools for digital systems have lost their importance because of the complexity reasons Traditional Stuck-at Fault (SAF) model does not quarantee the quality for deep-submicron technologies New solutions: The complexity can be reduced by raising the abstraction levels from gate to RTL, ISA, and behavioral levels –But this moves us even more away from the real life of defects (!) To handle adequately defects in deep-submicron technologies, new fault models and defect-oriented test generation methods should be used –But, this is increasing even more the complexity (!) To get out from the deadlock, these two opposite trends should be combined into hierarchical approaches

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 15 Fault and defect modeling Defects, errors and faults An instance of an incorrect operation of the system being tested is referred to as an error The causes of the observed errors may be design errors or physical faults - defects Physical faults do not allow a direct mathematical treatment of testing and diagnosis The solution is to deal with fault models System Component Defect Error Fault

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 16 Transistor Level Faults Stuck-at-1 Broken (change of the function) Bridging Stuck-open  New State Stuck-on (change of the function) Short (change of the function) Stuck-off (change of the function) Stuck-at-0 SAF-model is not able to cover all the transistor level defects How to model transistor defects ?

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 17 Mapping Transistor Faults to Logic Level Short x1x1 x2x2 x3x3 x4x4 x5x5 y Generic function with defect: Function: Faulty function: A transistor fault causes a change in a logic function not representable by SAF model Defect variable: d =d = 0 – defect d is missing 1 – defect d is present Mapping the physical defect onto the logic level by solving the equation:

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 18 Mapping Transistor Faults to Logic Level Short x1x1 x2x2 x3x3 x4x4 x5x5 y Test calculation by Boolean derivative: Generic function with defect: Function: Faulty function:

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 19 Functional Fault vs. Stuck-at Fault No Full SAF-TestTest for the defect x1x1 x2x2 x3x3 x4x4 x5x5 x1x1 x2x2 x3x3 x4x4 x5x Full 100% Stuck-at-Fault-Test is not able to detect the short: The full SAF test is not covering any of the patterns able to detect the given transistor defect  Functional fault

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 20 Defect coverage for 100% Stuck-at Test Results: the difference between stuck-at fault and physical defect coverages reduces when the complexity of the circuit increases (C2 is more complex than C1) the difference between stuck-at fault and physical defect coverages is higher when the defect probabilities are taken into account compared to the traditional method where all faults are assumed to have the same probability

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 21 Generalization: Functional Fault Model Constraints calculation: y Component F(x 1,x 2,…,x n ) Defect WdWd Component with defect: Logical constraints Fault-free Faulty Fault model: (dy,W d ), (dy,{W k d }) Constraints: d = 1, if the defect is present

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 22 Fault Table: Mapping Defects to Faults

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 23 Functional Fault Model for Stuck-ON Stuck-on x1x1 x2x2 Y V DD V SS x1x1 x2x2 NOR gate Conducting path for “10” RNRN RPRP x1x1 x2x2 yydyd Z: V Y 1100 Condition of the fault potential detecting:

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 24 Functional Fault Model for Stuck-Open Stuck-off (open) x1x1 x2x2 Y V DD V SS x2x2 NOR gate No conducting path from V DD to V SS for “10” x1x1 Test sequence is needed: 00,10 x1x1 x2x2 yydyd Y’ 1100 t x 1 x 2 y

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 25 Functional Fault Model Example: Bridging fault between leads x k and x l The condition means that in order to detect the short between leads x k and x l on the lead x k we have to assign to x k the value 1 and to x l the value 0. xkxk xlxl x* k d Wired-AND model x k *= f(x k,x l,d)

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 26 Functional Fault Model Example: x1x1 x2x2 x3x3 y & & x1x1 x2x2 x3x3 y & & & Equivalent faulty circuit: Bridging fault causes a feedback loop: Sequential constraints: A short between leads x k and x l changes the combinational circuit into sequential one t x 1 x 2 x 3 y

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 27 First Step to Quality How to improve the test quality at the increasing complexity of systems? First step to solution: Functional fault model was introduced as a means for mapping physical defects from the transistor or layout level to the logic level System Component Low level k WFkWFk WSkWSk Environment Bridging fault Mapping High level

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 28 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect- orientation Decision Diagrams (beyond BDDs) Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation Overview of tools developed at D&T Lab

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 29 Register Level Fault Models K: ( If T,C) R D  F(R S1, R S2, … R Sm ),  N RTL statement: K- label T- timing condition C- logical condition R D - destination register R S - source register F- operation (microoperation)  - data transfer  N- jump to the next statement Components (variables) of the statement: RT level faults: K  K’- label faults T  T’- timing faults C  C’- logical condition faults R D  R D - register decoding faults R S  R S - data storage faults F  F’- operation decoding faults  - data transfer faults  N - control faults (F)  (F)’ - data manipulation faults

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 30 Fault Models for High-Level Components Decoder: - instead of correct line, incorrect is activated - in addition to correct line, additional line is activated - no lines are activated Multiplexer ( n inputs log 2 n control lines): - stuck-at - 0 (1) on inputs - another input (instead of, additional) - value, followed by its complement - value, followed by its complement on a line whose address differs in 1 bit Memory fault models: - one or more cells stuck-at - 0 (1) - two or more cells coupled

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 31 Fault models and Tests Dedicated functional fault model for multiplexer: –stuck-at-0 (1) on inputs, –another input (instead of, additional) –value, followed by its complement –value, followed by its complement on a line whose address differs in one bit Functional fault model Test description

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 32 Faults and Test Generation Hierarchy Circuit Module System Network of gates Gat e Functional approach F ki Test F k W F ki W S F Test W F k W S k Structural approach Network of modules W d ki Interpretation of W F k : - as a test on the lower level - as a functional fault on the higher level Higher Level Module Component Lower level kiki W F ki W S ki Environment Bridging fault k WFkWFk

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 33 Hierarchical Defect-Oriented Test Analysis BDDs DDs

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 34 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation Decision Diagrams (beyond BDDs) Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation Overview of tools developed at D&T Lab

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 35 Binary Decision Diagrams x1x1 x2x2 y x3x3 x4x4 x5x5 x6x6 x7x7 0 1 Simulation: Boolean derivative: 1 0 Functional BDD

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 36 Elementary Binary Decision Diagrams Elementary BDDs: 1 x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 & x2x2 x3x3 y x1x1 x1x1 x2x2 x3x3 1 x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 + x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 yx2x2 x3x3 Adder NOR AND OR

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 37 Building a SSBDD for a Circuit & 1 1 x1x1 x2x2 x3x3 x 21 x 22 y a b a b y a x1x1 x 21 b x 22 x3x3 a y x3x3 y x3x3 x1x1 x 21 DD-library: Superposition of DDs  Superposition of Boolean functions: Given circuit: Compare to SSBDD Structurally Synthesized BDDs: ba

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 38 Representing by SSBDD a Circuit & & & & & & & a b c d e y Macro y 0 1 y = c y e y = c y  e y = x 6,e,y x 73,e,y  d ey b ey y = x 6 x 73  ( x 1  x 2 x 71 ) ( x 5  x 72 ) Structurally synthesized BDD for a subcircuit (macro) To each node of the SSBDD a signal path in the circuit corresponds

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 39 Fault modeling on SSBDDs The nodes represent signal paths through gates Two possible faults of a DD-node represent all the stuck-at faults along the signal path & & & & & & & a b c d e y Macro y 0 1 Test pattern: y

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 40 High-Level Decision Diagrams y 4 y 3 y 1 R 1 + R 2 IN + R 2 R 1 * R 2 IN* R 2 y 2 R  0 R 2 IN R Superposition of High-Level DDs: A single DD for a subcircuit R2R2 R 2 + M 3 Instead of simulating all the components in the circuit, only a single path in the DD should be traced M1M1 M2M2

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 41 High-Level Decision Diagrams A B C M ADR MUX 1 2 CC CON D Control Path Data Path  / FF y x q q z z 1 z 2 A digital system: System is partitioned into 4 subcircuits, each represented by a DD

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 42 High-Level DDs Digital system:

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 43 High-Level Vector Decision Diagrams 3,4 0 2 q q  1  4 x A  2 1  5 x B  3 A q x A B + C  A x C  C + B 0 4 x A A + C B q x A B + C  B C 14 2 q x A 1 0 x B A + B  C 0 x C x A 1 x C 3 0 M=A.B.C.q 1 1 q x A 0 q A i B’ + C’ #1 q B i B’ + C’ #2 0 q A i  A’ + 1 #4 2 1 x B q C i  C’ #3 0 q C i A’ + B’ #5 3 1 x C q A i B’ +  C’ #5 0 q C i A’ + B’ #5 4 1 x C q C i  C’ #5 0 B A i A’ + B’+C’ x A 0 q #5  B’ q B i  #5 A system of 4 DDsVector DD

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 44 Fault Modeling on High Level DDs High-level DDs (RT-level): Terminal nodes represent: RTL-statement faults: data storage, data transfer, data manipulation faults Nonterminal nodes represent: RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding, control faults

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 45 Two trends: high-level modeling –to cope with complexity low-level modeling –to cope with physical defects, to reach higher acuracy Hierarchical Diagnostic Modeling Boolean differential algebra BDD-s High-Level DD-s

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 46 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation Decision Diagrams (beyond BDDs) Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation Overview of tools developed at D&T Lab

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 47 Hierarchical Test Generation In high-level symbolic test generation the test properties of components are often described in form of fault-propagation modes These modes will usually contain: –a list of control signals such that the data on input lines is reproduced without logic transformation at the output lines - I-path, or –a list of control signals that provide one-to-one mapping between data inputs and data outputs - F-path The I-paths and F-paths constitute connections for propagating test vectors from input ports (or any controllable points) to the inputs of the Module Under Test (MUT) and to propagate the test response to an output port (or any observable points) In the hierarchical approach, top-down and bottom-up strategies can be distinguished

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 48 Hierarchical Test Generation Approaches A B C D a D c A = ax D: B = bx C = cx A B C D’ a’x d’x c’x A = a’x D’ = d’x C = c’x a,c,D fixed x - free a’ c’ a Bottom-up approach:Top-down approach: a’,c’,D’ fixed x - free System Module c

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 49 Hierarchical Test Generation Approaches Bottom-up approach: Pre-calculated tests for components generated on low-level will be assembled at a higher level It fits well to the uniform hierarchical approach to test, which covers both component testing and communication network testing However, the bottom-up algorithms ignore the incompleteness problem The constraints imposed by other modules and/or the network structure may prevent the local test solutions from being assembled into a global test The approach would work well only if the the corresponding testability demands were fulfilled A B C D a D c A = ax D: B = bx C = cx a,c,D fixed x - free a System Module c

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 50 Hierarchical Test Generation Approaches Top-down approach has been proposed to solve the test generation problem by deriving environmental constraints for low-level solutions. This method is more flexible since it does not narrow the search for the global test solution to pregenerated patterns for the system modules However the method is of little use when the system is still under development in a top-down fashion, or when “canned” local tests for modules or cores have to be applied Top-down approach: A B C D’ a’x d’x c’x A = a’x D’ = d’x C = c’x a’ c’ a’,c’,D’ fixed x - free System Module

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 51 Hierarchical Test Generation with DDs Single path activation in a single DD Data function R 1 * R 2 is tested Data path Decision Diagram Hierarhical test generation with DDs: Scanning test (defect-oriented) Control: y 1 y 2 y 3 y 4 = x032 Data: For all specified pairs of (R 1, R 2 ) Test program: Low level test data (constraints W)

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 52 Test Generation with High Level DDs y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R  0 R 2 IN R Multiple paths activation in a single DD Control function y 3 is tested Data path Decision Diagram High-level test generation with DDs: Conformity test (High-level faults) Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 2  IN  R 1  R 1 * R 2 Test program: Activating high-level faults:

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 53 Gate-level Test Generation Structural gate-level testing: Path activation & & & & & & & a b c d e y Macro D D D D D Fault sensitisation: x 7,1 = D Fault propagation: x 2 = 1, x 1 = 1, b = 1, c = 1 Line justification: x 7 = D = 0: x 3 = 1, x 4 = 1 b = 1: (already justified) c = 1: (already justified) Symbolic fault modeling: D = 0 - if fault is missing D = 1 - if fault is present Test pattern

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 54 Defect-Oriented Test Generation Test generation for a bridging fault: & & & & & & & a b c d e y Macro D D D D D Fault manifestation: W d = x 6 x 7 = 1: x 6 = 0, x 7 = 1, x 7 = D Fault propagation: x 2 = 1, x 1 = 1, b = 1, c = 1 Line justification: b = 1: x 5 = 0 y Component F(x 1,x 2,…,x n ) Defect WdWd Activate a path Bridge between leads 7 3 and 6 WdWd 0 1

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 55 Test Generation with SSBDDs & & & & & & & a b c d e y Macro y 0 1 Test pattern for the node 7 1 at the constraint W d = x 6 x 7 = 1: y Defect: dx 7 =1: x 7 =0 No fault: dx 7 =0: x 7 =1 Defect W d manifestation: W d = x 6 x 7 = 1: x 6 = 0, x 7 = 1, x 7 = D Functional Fault dx 7 propagation: x 1 = 1, x 2 = 1, x 5 = 0 Bridge between leads 7 and 6: (dx 7,W d ) (dx 7,W d )

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 56 Test Generation for RTL Digital Systems y 3  0 CR’ 2 C y 2 2 A 2R’ 2 y 1 R’ 1 3 B F(B,R’ 3 ) A A A  R’ 1  0  0  0 2 Y,R 3 R R 1 C R’ 1 1  C+R’ 2 R’ R 3 R 2  F R 1 A B C Y y 2 A y 3 y 1 s System model Data path Control path q’  1001 q y 1 y 2 y 3  R’ 2 =0 1 0 #2120   3021  4211 

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 57 Test Generation for RTL Digital Systems y 3  0 CR’ 2 C y 2 A 2R’ 2 y 1 R’ 1 3 B F(B,R’ 3 ) A A A  R’ 1  0  0  0 2 Y,R 3 R R 1 C R’ 1 1  C+R’ 2 R’ Transparency functions on Decision Diagrams: Y = C  y 3 = 2, R 3 ’ = 0 C - to be tested R 1 = B  y 1 = 2, R 3 ’ = 0 R 1 - to be justified + R 3 R 2  F R 1 A B C Y y 2 A y 3 y 1 s High-level path activation on DDs 0 2

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 58 Test Generation for RTL Digital Systems Test generation steps: Fault manifestation Fault-effect propagation Constraints justification y 3 =2 R’ 2 =0 y 2  0 R 3 = D= D A  R’ 1 A = D= D 1 1 = D= D 2 B = D= D 2 3 =0 y 1 =2=2 y 3  0 C = D= D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 High-level test generation for data-path (example): D D1D1 D2D2

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 59 Test Generation for RTL Digital Systems Test generation step: Fault-effect propagation y 3 = 2= 2 R’ 2 = 0= 0 y 2 = 0  0 R 3 =D A  R’ 1 A =D 1 R’ 1 =D 2 B 2 R’ 3 = 0= 0 y 1 = 2= 2 y 3 = 0  0 C =D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 y 3  0 CR’ 2 C 2 Y,R C+R’ 2 R’ 3 q’  1001 q y 1 y 2 y 3  R’ 2 =0 1 0 #2120   3021  4211  D D

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 60 Test Generation for RTL Digital Systems y 3  0 CR’ 2 C 2 Y,R y 1 R’ 1 3 B F(B,R’ 3 )  0 R C+R’ 2 R’ 3 y 2 2 A 2R’ 2  0R R’ 2 Path activation procedures on DDs: y 3 =2 R’ 2 =0 y 2  0 R 3 =D A  R’ 1 A =D 1 R’ 1 =D 2 B 2 R’ 3 =0 y 1 =2=2 y 3  0 C =D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 q’  1001 q y 1 y 2 y 3  R’ 2 =0 1 0 #2120   3021  4211  Test generation step: Line justification Time: t-1

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 61 Test Generation for RTL Digital Systems Symbolic test sequence: y 3 =2 R’ 2 =0 y 2  0 R 3 =D A  R’ 1 A =D 1 R’ 1 =D 2 B 2 R’ 3 =0 y 1 =2=2 y 3  0 C =D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 High-level test generation example:

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 62 Test Generation for Microprocessors I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  A I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A High-Level DDs for a microprocessor (example): Instruction set: IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor:

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 63 Test Generation for Microprocessors High-Level DD-based structure of the microprocessor (example): IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: OUT R A IN I

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 64 Test Generation for Microprocessors IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Scanning test program for adder: Instruction sequence T = I 5 (R)I 1 (A)I 7 I 4 for all needed pairs of (A,R) OUT I4I4 A I7I7 A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 65 Test Generation for Microprocessors IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Conformity test program for decoder: Instruction sequence T = I 5 I 1 D I 4 for all D  I 1 - I 10  at given A,R,IN Data generation: Data IN,A,R are generated so that the values of all functions were different

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 66 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation Decision Diagrams (beyond BDDs) Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Hierarchical fault simulation Overview of tools developed at D&T Lab

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 67 Deductive Fault Simulation & & a c b y Fault list calculation: L a = L 4  L 5 L b = L 1  L 2 L c = L 3  L a L y = L b - L c L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) Gate-level fault list propagation L a – faults causing erroneous signal on the node a L y – faults causing erroneous signal on the output node y Library of formulas for gates

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 68 Deductive Fault Simulation with DDs Macro-level fault propagation: & & a c b y Fault list propagated: L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) y Fault list calculation on the DD L y = ( L 1  L 2 ) L y = ( L 1  L 2 ) - L 3 L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) Faults on the activated path: First order fault masking effect: Second order masking effect (tradeoff): There is a tradeoff possibility between the speed and accuracy When increasing the speed of simulation the results will be not accurate (pessimistic): less fault detected than in reality Activated faults Masking faults

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 69 Hierarchical fault simulation High-Level component High-Level component High-Level component Sequence of patterns P: First Pattern R: Faults Set of patterns With faults P;P 1 (R 1 )…P n ( R n ) Set of patterns with faults P;P 1 (R 1 )…P m ( R m ) P: Pattern Set of patterns with faults P;P 1 (R 1 )…P n ( R n ) System

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 70 Hierarchical fault simulation

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 71 Hierarchical fault simulation Definition of the complex pattern: D = {P, (P 1,R 1 ), …, (P k, R k )} P is the fault-free pattern (value) P i (i = 1,2,..., k) are faulty patterns, caused by a set of faults R i All the faults simulated causing the same faulty pattern P i are put together in one group R i R 1 - R k are the propagated fault groups, causing, correspondingly, the faulty patterns P 1 - P k

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 72 Fault Simulation with DD-s Fault propagation through a complex RT-level component q xAxA xcxc B C A D q = {1, 0 (1,2,5), 4 (3,4)}, D xA = {0, 1 (3,5)}, D xC = {1, 0 (4,6)}, D A = {7, 3 (4,5,7), 4 (1,3,9), 8 (2,8)}, D B = {8, 3 (4,5), 4 (3,7), 6 (2,8)}, D C = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)}. Decision diagram New D A to be calculated Sub-system for A A q xAxA B + C A xCxC A + C 04 xAxA A 0 xCxC A - 1 A + B

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 73 Fault Simulation with DD-s Fault propagation through a complex RT-level component D q = {1, 0 (1,2,5), 4 (3,4)}, D xA = {0, 1 (2,5)}, D xC = {1, 0 (3,4)}, D A = {7, 3 (3,4,5,7), 4 (1,9), 8 (2,8)}, D B = {8, 3 (4,5), 4 (3,7), 6 (2,8)}, D C = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)}. q’x A 1 (1,2,3,4,5) 0 (1,2,3,4,5) A’+1 8 (  ) 9 (8) 5 (9) B’+C’ 0 (1,2,5) 8(  ) + 1(1) = 9(1) 6(2) + 2(2) = 8(2) 3(5) + 4(  ) = 7(5) x A x C A’ 4 (3,4) 0 (4) 1 (3) 0 (4) ) 1 1 New complex vector for A: D A = {8, 3(4), 4(3,7), 5(9), 7(5), 9(1,8)} This fault is masked 8(2) 4 (7) A’ 4(3)

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 74 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation Decision Diagrams (beyond BDDs) Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Overview of tools developed at D&T Lab

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 75 DECIDER: Hierarchical ATPG R 2 M 3 e + M 1 a * M 2 b   R 1 IN    c d y 1 y 2 y 3 y 4 y 4 y 3 y 1 R 1 +R 2 + R 2 R 1 *R 2 IN*R 2 y 2 R  0 R 2 IN R Modules or subcircuits are represented as word-level DD structures Logic Synthesis Scripts Design Compiler (Synopsys Inc.) Gate Level Descriptions SSBDD Synthesis SSBDD Models of FUs Hierarchical ATPG RTL Model (VHDL) FU Library (VHDL) FU Library (DDs) RTL DD Synthesis Test patterns RTL DD Model

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 76 ATPG: Experimental Results Reference ATPGs: HITEC - T.M. Nierman, J.H. Patel, EDAC, 1991 GATEST - E.M.Rudnick et al., DAC, 1994 TTU: DET/RAND - hierarchical deterministic- random ATPG GENETIC - gate-level ATPG based on genetic algorithms

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 77 TURBO-TESTER: Low-Level TPG Tools Test Generation BIST Simulation Methods: Deterministic Random Genetic Methods: BILBO CSTP Store/Generate Design Test Levels: Gate Macro Fault Simulation Methods: Single fault Parallel Deductive Fault Table Fault models: Stuck-at-faults Stuck-opens Delay faults Test Optimization Fault Diagnosis Fault Location

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 78 Conclusions Physical defects can be formally mapped to the logical level by Boolean differential calculus Functional fault model is a universal means for mapping test results from lower levels to higher levels, giving a formal basis for hierarchical approaches to test generation and fault simulation Decision diagrams is a suitable tool which can be used successfully both, on the logic level, and also on higher register transfer or behavioral levels

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 79 References 1.S.Mourad, Y.Zorian. Principles of Testing Electronic Systems. J.Wiley & Sons, Inc. New York, 2000, 420 p. 2.M.L.Bushnell, V.D.Agrawal. Essentials of Electronic testing. Kluwer Acad. Publishers, 2000, 690 p. 3.M. Abramovici et. al. Digital Systems Testing & Testable Designs. Computer Science Press, 1995, 653 p. 4.S. Minato. Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Academic Publishers, 1996, 141 p. 5.R.Ubar. Test Synthesis with Alternative Graphs. IEEE Design and Test of Computers. Spring, 1996, pp J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. JETTA: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp , R.Ubar, W.Kuzmicz, W.Pleskacz, J.Raik. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED’02, San Jose, California, March 26-28, 2001, pp T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Test Generation with Real Defects Coverage. Pergamon Press. J. of Microelectronics Reliability, Vol. 42, 2002, pp

Technical University Tallinn, ESTONIA Copyright by Raimund Ubar 80 References European Projects: –EEMCN, FUTEG, ATSEC, SYTIC, VILAB, REASON, eVIKINGS II Special thanks to: –EU project IST REASON –Cooperation partners: IISAS Bratislava, TU Warsaw –Colleagues: J.Raik, A.Jutman, E.Ivask, E.Orasson a.o. (TU Tallinn) Contact data: –Tallinn Technical University –Computer Engineering Department –Address: Raja tee 15, Tallinn, Estonia –Tel.: , Fax: – – ˇ raiub/