MMDAQ Content – Overview – Case study – adding support for VMM1 chips – Drawings (data flow, concurrency, error reporting, scalability, monitoring) 13 Feb 2013Marcin Byszewski, MMDAQ overview1 MMDAQ is the data acquisition software used by Micromegas ATLAS upgrade R&D during test beam periods and in the laboratories. Apart from what is presented here it also has satellite programs like offline event browser, data preparation (filtering, clusterisation).

MMDAQ During the design of the MMDAQ no assumptions were taken on electronics type or readout configuration. Any combination of data sources (Chips, FEC, SRU) – (multithreading, dynamic dispatch) Event building on available variables – (Trigger#, SRS Time Stamp, EoE FAFA frame) Client - Server and Detached GUI – (by interprocess communication) Scalability – (multithreading, data buffering design limiting locking) XML Configuration 13 Feb 2013Marcin Byszewski, MMDAQ overview2

13 Feb 2013Marcin Byszewski, MMDAQ overview3 Data validation and monitoring requires that we understand data format. Each new electronics type requires its own class representation Network Device, Chip, Channel

Case study: integration of VMM1 During 2012 test beam runs we have acquired data from a heterogeneous readout system using the MMDAQ. It had to be adapted from reading SRS-FECs with 16 APV25 chips each (UDP protocol) to being able to read tracking information from VMM1 chips connected to BNL-DAQ boards and VMM1 trigger data from BNL-FPGA evaluation board. Challenges and solutions were: Synchronisation mechanism of data sources, and event building – Trigger number embedded in data Handling of multiple sources of data - each VMM1 board is a UDP data source (= SRS-FEC), albeit with relatively low data rate – MMDAQ-FEC (MMDAQ representation of SRS-FEC) support multiple data sources to limit thread use for low rate data sources VMM1 trigger evaluation board uses TCP protocol – Special MMDAQ-FEC for TCP protocol 13 Feb 2013Marcin Byszewski, MMDAQ overview4

Case study: integration of VMM1 Multiple data sources support for MMDAQ-FEC classes – Option 1: Each VMM1 board represented as MMDAQ-FEC in MMDAQ (many treads) – Option 2: MMDAQ-FEC serves multiple VMM1 (one thread for many VMM1s) 13 Feb 2013Marcin Byszewski, MMDAQ overview5 Configuration file Option 1: BNL VMM Configuration file Option 2: BNL VMM VMM

Case study: integration of VMM1 13 Feb 2013Marcin Byszewski, MMDAQ overview6 FEC APV25 processing FEC APV25 processing FEC BNL processing FEC BNL processing CSrsChipApv NIC UDPReceiver Identify data source Verify data source UDPReceiver Identify data source Verify data source CSrsChipVmm RootWriter APV tree VMM tree ApvChannel (processing) ApvChannel (processing) VMMChannel (processing is no-op) VMMChannel (processing is no-op) UDP packets Support VMM1-BNL-DAQ: By providing 3 derived classes: CSrsChipBnl : public CSrsChip CSrsChannelBnl : public CSrsChannel CRootTreeFillerBnl: public CRootTreeFiller and implementing functions for chip-specific data handling (mostly none for VMM1) TCPReceiver (For VMM1 trigger analysis) TCPReceiver (For VMM1 trigger analysis) TCP packets (…)

DRAWINGS concurrency, scalability 13 Feb 2013Marcin Byszewski, MMDAQ overview7

Receiver SRS data source NIC Input buff De code UDP De code UDP FEC UDP Buffe r Process data (ZS) Process data (ZS) Chip EvID, channels Chip EvID, channels Processed data (channels) eventID Writer (RootWriter) eventID Data Flow Event Builder Chip type -> Timeout, completeness Event Builder Chip type -> Timeout, completeness EvID Timeout / ready 13 Feb 2013Marcin Byszewski, MMDAQ overview8 UDP packets with RAW data RAW Processed data (channels) Receiver, FEC, Chip, Writer are designed to be extensible by inheritance.

UDPReceiver SRS data source NIC Input buff De code UDP De code UDP FEC UDP Buffe r Process data (ZS) Process data (ZS) Chip EvID, channels Chip EvID, channels Data (channels) eventID RootWriter eventID Concurrency Event Builder Chip type -> Timeout, completeness Event Builder Chip type -> Timeout, completeness EvID Timeout / ready 1 pool 1 13 Feb 2013Marcin Byszewski, MMDAQ overview9 Threads / thread pools are represented by distinct colouring.

UDPReceiver SRS data source NIC Input buff De code UDP De code UDP FEC UDP Buffe r Process data (ZS) Process data (ZS) Chip EvID, channels Chip EvID, channels Event Builder Chip type -> Timeout, completeness Event Builder Chip type -> Timeout, completeness Data (channels) eventID RootWriter eventID EvID Error reporting Timeout / ready Timed-out/missing fragment Queue overflow Bad ip Queue overflow Bad data Bad chip id Queue overflow 13 Feb 2013Marcin Byszewski, MMDAQ overview10

NIC FEC Chip EvID, channels Chip EvID, channels Data (channels) eventID RootWriter eventID Scalability Event Builder Chip type -> Timeout, completeness Event Builder Chip type -> Timeout, completeness EvID Timeout / ready 1 pool 1 NIC UDPReceiver 1+1 lock 13 Feb 2013Marcin Byszewski, MMDAQ overview11 40MB/s (300Hz) 15MB/s per NIC (1.8kHz,16x 520B) Very preliminary

UDPReceiver SRS data source NIC Input buff De code UDP De code UDP FEC UDP Buffe r Process data (ZS) Process data (ZS) Chip EvID, channels Chip EvID, channels Data (channels) eventID RootWriter eventID Monitoring Event Builder Chip type -> Timeout, completeness Event Builder Chip type -> Timeout, completeness EvID Timeout / ready 13 Feb 2013Marcin Byszewski, MMDAQ overview12 Publisher request stats Monitoring based on Existing event display program