Chapter 0 – Week 2 Combinational Logic Design. What have been discussed Design hierarchy –Top – down –Bottom – up CAD HDL Logic synthesis.

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Presentation transcript:

Chapter 0 – Week 2 Combinational Logic Design

What have been discussed Design hierarchy –Top – down –Bottom – up CAD HDL Logic synthesis

Analysis Procedure Analysis –To determine the function of a circuit Derive Boolean equation Derive truth table

Analyze this logic diagram T1 T3 T2 T4 T5

Boolean Equation T1 = T2 = T3 = T4 = T5 = F1 = F2 =

Analyze this Binary Adder R1 R2 R3

Truth Table XYZ CCR1R2R3S

Logic Simulation A fast and accurate method of analyzing a combinational circuit Using simulator software Results : –Waveforms –A complete truth table –Part of a truth table

Logic Simulation How is the circuit described in the software ? –Schematics –HDL

Schematic for Binary Adder in Xilinx

Waveforms for Binary Adder

Point to ponder…. Why do we compare the simulation results vs the theoretical results?

Design Procedure Given : Specifications of the problem 1.Determine input & output 2.Derive truth table 3.Obtain Boolean equation (K-map) 4.Draw schematics 5.Verify design

Design of BCD to Excess – 3 Code Converter Specifications : Input in decimal numbers, 0 – 9, in binary form Output is excess – 3 code E.g –Decimal = 5 (101) –Excess – 3 code = = 8 (1000)

BCD  Excess – 3 Step 1. –Input : –Output :

BCD  Excess – 3 Step 2 : Truth Table

BCD  Excess – 3 Step 3 : Boolean equation

BCD  Excess – 3 Step 4 : Schematic diagram

BCD  Excess – 3 Step 5 : Verify that schematic diagram agrees with truth table

Design of BCD to 7 – segment decoder Specifications : Input in decimal numbers, 0 – 9, in binary form 7 Outputs – to display input number

7 – segment Display

BCD to 7 –segment decoder Step 1 :

BCD to 7 –segment decoder Step 2 : Truth Table

Exercise A traffic light system has the following specifications for a part of its controller. There are 3 parallel lanes, each with its own red / green light. One of these lanes, the priority lane, is given priority for a green light over the other 2 lanes. On the other hand, an alternating scheme is used for the other 2 lanes, which are left and right lane. Design the circuit that determines which light is to be green at a particular time. The specifications for the controller are as follows :

Exercise Inputs : PS – Priority Lane Sensor ( car present = 1; car absent = 0 ) LS – Left Lane Sensor ( car present = 1; car absent = 0 ) RS – Right Lane Sensor ( car present = 1; car absent = 0 ) AS – Alternating Signal ( select left = 1; select right = 0 ) Outputs : PL – Priority Lane Light ( green = 1; red = 0 ) LL – Left Lane Light ( green = 1; red = 0 ) RL – Right Lane Light ( green = 1; red = 0 )

Exercise 1.If there is a car in the priority lane, PL = 1. 2.If there are no cars in the priority lane and the right lane, and there is a car in the left lane, LL = 1. 3.If there are no cars in the priority lane and in the left lane, and there is a car in the right lane, RL = 1. 4.If there is no car in the priority lane, there are cars in both the left and right lanes, and AS = 1, then LL = 1. 5.If there is no car in the priority lane, there are cars in both the left and right lanes, and AS = 0, then RL = 1. 6.If any PL, LL or RL is not specified to be 1 above, then it has value 0.

The End