Microelectronics User Group Meeting TWEPP 2013, Perugia, IT 26/9/2013

Agenda “News on foundry access services via CERN” by Kostas Kloukinas (CERN) (15’) “Status of 65nm technology access, distribution and IP block development.” by Sandro Bonacini (CERN) (25’) “Open Discussion” 26/9/13 2

News on foundry access services via CERN Kostas Kloukinas TWEPP 2013, Perugia, IT 26/9/2013

Supported Technologies CMOS 8RF-LM Low cost technology for Large Digital designs CMOS 8RF-LM Low cost technology for Large Digital designs CMOS 8RF-DM Low cost technology for Analog & RF designs CMOS 8RF-DM Low cost technology for Analog & RF designs BiCMOS 8WL-HP High Performance technology for demanding RF designs CMOS 9SF LP/RF High performance technology for dense designs CMOS 9SF LP/RF High performance technology for dense designs 130nm CMOS 90nm CMOS 26/9/13 CMOS 65nm High performance technology for dense designs CMOS 65nm High performance technology for dense designs 65nm CMOS CMOS 6SF Legacy designs CMOS 6SF Legacy designs 250nm CMOS 4 130nm CMOS CMOS 130nm Cost efficient technology for Analog & RF designs CMOS 130nm Cost efficient technology for Analog & RF designs Foundry A Foundry B Active technology nodes: Legacy technology: CMOS6SF 250nm Mainstream technology: CMOS8RF 130nm  95% of ASIC projects on DM variant Advance technology: CMOS 65nm  For LHC upgrade applications. Alternate technology: CMOS 130nm

Technical Support for Foundry A 26/9/13 5 Foundry Physical IP vendors CAE Tools vendors CERN CAE tools & technology support Cadence VCAD design services CERN designers External designers Compiles and Distributes the 130nm Mixed Signal Design kit Provide maintenance and technical support to the collaborating institutes.

130 nm Mixed Signal Kit Distribution US Brookhaven Lab. Columbia University Fermilab Lawrence Berkeley Lab. Rutgers Univ. Univ. of Chicago Univ. of Hawaii Univ. of Pennsylvania Ohio State University SMU,Dallas Santa Cruz Institute US Brookhaven Lab. Columbia University Fermilab Lawrence Berkeley Lab. Rutgers Univ. Univ. of Chicago Univ. of Hawaii Univ. of Pennsylvania Ohio State University SMU,Dallas Santa Cruz Institute Germany Bergische Universität Wuppertal DESY, Hamburg Institut der Universitaet Heidelberg Max-Plank-Institute fur Physik Max-Plank-Institute Halbleiterlabor Forschungszentrum Julich University of Siegen Universität Bonn Germany Bergische Universität Wuppertal DESY, Hamburg Institut der Universitaet Heidelberg Max-Plank-Institute fur Physik Max-Plank-Institute Halbleiterlabor Forschungszentrum Julich University of Siegen Universität Bonn Italy INFN Rome INFN Torino INFN Bologna INFN Bari INFN Cagliari Univ. of Bergamo Univ. of Pisa Univ. of Pavia Polytecnico di Milano Italy INFN Rome INFN Torino INFN Bologna INFN Bari INFN Cagliari Univ. of Bergamo Univ. of Pisa Univ. of Pavia Polytecnico di Milano France CEA SACLAY, Paris IN2P3, Paris LPNHE, Paris IPNL, Lyon IPHC, Strasbourg LPSC, Grenoble LAPP, Annecy LPC, Clermont-Ferrand CPPM, Marceille INPG, Grenoble France CEA SACLAY, Paris IN2P3, Paris LPNHE, Paris IPNL, Lyon IPHC, Strasbourg LPSC, Grenoble LAPP, Annecy LPC, Clermont-Ferrand CPPM, Marceille INPG, Grenoble UK Rutherford Appleton Lab. Imperial College London University College London Oxford University UK Rutherford Appleton Lab. Imperial College London University College London Oxford University Portugal INESC, Porto LIP, Lisbon Portugal INESC, Porto LIP, Lisbon Spain Univ. of Barcelona IFAE, Barcelona IFIC, Valencia Spain Univ. of Barcelona IFAE, Barcelona IFIC, Valencia Netherlands NIKEF, Amsterdam Netherlands NIKEF, Amsterdam Poland AGH Univ. of Science & Tech. Poland AGH Univ. of Science & Tech. CERN 26/9/13 Switzerland Universite de Geneve Switzerland Universite de Geneve 6

130nm Mixed Signal Design Kit Mixed Signal Design kit in production: V1.8  Release date: 10/6/2011  Stable and fully functional.  No plans for foundry PDK releases in 2013  Digital back-end physical implementation flow scripts need updates to ensure compatibility with newer versions of CAE tools. Rad Tol. SRAM IP block available at CERN  Radiation Tolerant design, developed at CERN  40MHz, Dual Port, synchronous design  SRAM generator developed at CERN  Contact CERN to access SRAM generation 26/9/13 7

130nm Foundry Access Service 26/9/13 8 CERN Foundry Services CERN designers External designers Foundry MOSIS CERN organizes MPW runs among the collaborating institutes to help in keeping low the silicon prototyping costs.

130nm MPW activity CERN participates on all MOSIS MPW runs (4 runs/year) and organizes ad-hoc MPWs directly with the foundry for high volume and/or area demanding designs Prototyping and Engineering run costs are kept the same for the last 2 years. 26/9/13 Evolution of the Prototyping activity on CMOS8RF for the last 6 years CMOS8RF-DM (3-2-3) is the dominant metal stack 9

130nm CERN MPW in July /9/13 10 XFEL2 CBC2 TOFPET test structures Design Project. TDCpix NA62 Gigatracker pixel readout ABC130_0 ATLAS Tracker Si-strip readout ABC130_1 >> Reticle Size: X= 19,120, Y=20,400 Chips per Wafer: 60 Process Split MPW run Designprocess TDCpixno polyimide, ABC130_0 polyimide, ABC130_1polyimide, Submitted in August 2013 Expected delivery in October 2013 ABC130_0 ABC130_1 TDCpix

130nm Major Projects Gigabit Transceiver Project (GBT)  “GBLD” Gigabit Laser Driver chip final version in  “GBT-TIA” Transimpedance Amplifier chip in  “GBTX”, Transceiver chip, first prototype in 2009, second prototype in  “GBT-SCA”, Slow Control Adapter, first prototype in Design Projects for the XFEL Synchrotron facility  XFEL & DSSC ASIC designs  Prototype chips submitted in 2010, 2011,  DSSC full prototype submission scheduled for early CBC: CMS Tracker Front-End ASIC  First prototype submitted in 2010 MPW.  Second prototype submitted in 2012 MPW. S-Altro: ALICE TPC Readout ASIC  Submitted in 2010 on an MPW (24 wafers). NA62 Pixel Gigatracker detector  Test chips prototyped in  First prototype submitted in /9/13 11

130nm Major Projects FE-I4_B: ATLAS PIXEL ‘b-layer upgrade’  Engineering run (design area:19x20mm2) in  Production run of 96 wafers in  Post production order of 56 wafers in MEDIPIX project  MEDIPIX3_V1: 12 wafers in 2009  MEDIPIX3_V2: 12 wafers in 2010  MEDIPIX_RX: 48 wafers in 2012  TIMEPIX3: 1 st prototype run in /9/13 Medipix: Medical X-ray diagnosis with contrast enhancement and dose reduction 12

Foundry Services News Contract with Foundry A  Contract renewed for 3 years ( )  Same pricing conditions apply with some minor changes  Confidential Disclosure Agreement (CDA) with institutes will expire by the end of 2013 Renewal procedure has started Institute signatory authorities are already contacted by ACTION: verify that your institute has renewed the CDA with the foundry to maintain uninterrupted access to technology Contract with Foundry B  Foundry access via an intermediary silicon broker  Contract preparation is in the final stage  Long procedures for negotiating technology information disclosure legal terms and contractual pricing conditions for prototyping and production services  Contract covers a period of 5 years ( )  More information on the next presentation by Sandro Bonacini. 26/9/13 13

Foundry Services News New member in CERN foundry services team:  Gert Olesen Responsible for coordinating all the logistics procedures (administrative, financial, handling) for the foundry access operations Contacts at CERN for foundry services  Gert Olesen  Kostas Kloukinas  Generic address: Please use this address for foundry access 26/9/13 14

MPW Call for Interest Please contact for participation to:  Forthcoming MPW runs: CMOS8RF (130nm)  MOSIS MPW, Nov. 18, 2012 Inform CERN about your future submission plans as early as possible  For prototyping or small volume production  Indicate your request for special process options (passivation, C4 bumping, DM/LM metalization)  To help us plan ahead common MPW runs 26/9/13 15

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