Introduction to Hardware Verification ECE 598 SV Prof. Shobha Vasudevan

Class logistics Timing change issue Clarification on registration New time and location Seminar course Paper reading and summaries Homeworks Project

Homeworks Different algorithms implemented in publicly available verification tool (ABC) Verification of different small designs using tools

Project Implementing modifications to verification algorithms Verifying a domain specific application/model using ABC

Difference between ECE 598SV and ECE 584 Continuous vs Discrete systems Control and computation Hybrid automata etc Focus of ECE 598SV is on finite state systems Modeling and algorithms are scalable Practically deployed in industrial tools Scales to millions of hardware elements

What is verification? Specification is desired behavior Implementation is a concrete execution of specification Verification is the process of checking intent against execution

The grand challenge of verification Design verification is the task of establishing that a given design accurately implements the intended behaviour. In current projects, verification engineers outnumber designers, with this ratio reaching two or three to one for the most complex designs. Design conception conception and implementation implementation are becoming becoming mere preludes preludes to the main activity of verification... Without major breakthroughs, verification will be a non-scalable, show- stopping barrier to further progress in the semiconductor industry. Int. Technology Roadmap for Semiconductors, 2006

Verification landscape Method to specify intent Document in English Properties in a formal logic Executable specification Implementation to check the intent Model of the implementation Actual implementation itself Method to check the implementation against specification Automatic exhaustive algorithms Non-exhaustive algorithms Manual methods

Static vs dynamic verification Model: static verification Actual implementation: Runtime verification

Specification Documentation in English Executable specification Formal specifications in logic

Implementation Different kinds of models and their treatment Amount of information in the model determines the abstraction level Tradeoff between adding information and scalability

What does exhaustive/non exhaustive mean? Depending on abstraction, checking behavior with 100% guarantee is exhaustive Less than 100% guarantee is non-exhaustive Scalability tradeoff with completeness

Hardware verification paradigms Automatic exhaustive Model checking and its variations Equivalence checking Non exhaustive Simulation based Hybrid Manual Theorem proving etc

Simulation based verification Unit simulation is the most extensive phase of verification Unit: FPU, LSU, ISU etc. Most bugs are found here Once stable, units integrated into core level simulation Can execute real programs Directed input stimulus generation Functional verification of architectural properties System simulation is with multiple cores and chips, IO and memory System level hookup and functionality issues Powering on, booting etc can be checked at this stage

Simulation based verification Advantages Scalable; nearly linear time wrt design size Finds most of the common bugs and many of the subtle bugs Lot of legacy technology and infrastructure that has worked for generations Disadvantages Ad-hoc, never know if you caught all the bugs Some bugs are found too late Some bugs are never found before tape out Directed input stimulus, constrained random input stimulus, monitors, assertions, coverage points

Formal verification Mathematical or logical reasoning applied to the checking problem Used for bug finding and proving properties High confidence in the system Used in conjunction with simulation and called semi-formal

Role of verification in hardware Hardware cycle Pre-Silicon verification Formal Simulation Post Silicon validation Runtime verification Testing

Hardware design cycle