CSI-2111 Structure of Computers Ipage Combinational Circuits  Objectives : To recognize the principal types of combinational circuits  Adders and subtracters  Decoders, comparators, converters  Multiplexers and demultiplexers  Logical programmable: ROM, PAL, PLA  Arithmetic logic unit (ALU)  Various combinations for their analysis and synthesis, and the synthesis of functions in general.

CSI-2111 Structure of Computers Ipage 5-2  Already discussed the adder (Chap. 2)  Subtracters –Half-subtracters, elementary –Adders/subtracters –Subtracters with several bits 5.1 Adders and Subtracters I D E B A

CSI-2111 Structure of Computers Ipage Decoders  Decode a binary word.  It has n inputs and m  2 n outputs. ABD 0 D 1 D 2 D Decoder 2 to D1D1 A D0D0 B D2D2 D3D3

CSI-2111 Structure of Computers Ipage 5-4 Synthesis with decoders  Any binary function f(x 1, x 2,..., x n ) can be realized simply by a n x 2 n decoder and an OR gate. –Example: Elementary adder Decoder with Enable ( E ) input –E allows enable/disable a decoder. –If E = 0, all the outputs are to 0. –Useful in the synthesis of large decoders

CSI-2111 Structure of Computers Ipage 5-5 Synthesis with decoders *  Elementary adder S (X, Y, Z) =  m ( 1, 2, 4, 7 ) C (X, Y, Z) =  m ( 3, 5, 6, 7 ) 3 x 8 decoder X Y Z S C

CSI-2111 Structure of Computers Ipage 5-6 Synthesis of large decoders x D 0 to D 7 z y x D 8 to D 15 z y w  4 x 16 decoder using two 3 x 8 decoders 3 x 8 decoder E x 8 decoder E

CSI-2111 Structure of Computers Ipage 5-7 Synthesis of large decoders *  4 x 16 decoder using 2 x 4 decoders 2 x 4 decoder 2020 E x 4 decoder 2020 E x 4 decoder 2020 E x 4 decoder 2020 E x 4 decoder 2020 E D 0 to D 3 z y D 4 to D 7 z y D 8 to D 11 z y D 12 to D 15 z y x w

CSI-2111 Structure of Computers Ipage Magnitude Comparators  Carry out the comparison of two binary numbers. –The comparator of binary numbers (A and B) of four bits to indicate if A>B, A B, A<B and A=B) allowing the sequence of the circuits to compare numbers of more than four bits (in cascade).

CSI-2111 Structure of Computers Ipage Code Converter  Achieves the conversion of information in one form of binary representation to another form of binary representation. –Examples:  1CF to 2CF  BCD to Excess-3  BCD to representation in 7 segments –As in a display –Various options (0 to 9, 0 to 9 with values indifferent for entries 10 to 15, 0 with F, etc.)

CSI-2111 Structure of Computers Ipage Multiplexers  Use Source 0 Source 1 Source 2 n -1 Destination 0 Destination 1 Destination 2 n MultiplexingDemultiplexing Un seul lien MultiplexDemultiplexer

CSI-2111 Structure of Computers Ipage 5-11 Multiplexers –Multiplexer (MUX) selects one out of 2 n inputs of information and directs it to the output. –Example: 4-to-1 Multiplexer. S 1 S 0 Y 00D 0 01D 1 10D 2 11D 3 MUX 4-to-1 S D1D1 Y D0D0 D2D2 D3D S1S S0S0

CSI-2111 Structure of Computers Ipage 5-12 Synthesis with multiplexer  That is to say a binary function f(x 1, x 2 …, x n ), its realization with a multiplexer is done according to the following procedure: 1. Develop the Truth Table of f. 2. If the multiplexer is rather large (2 n to 1 MUX)  Then not of problem. All is direct!  If not… use 2 n-1 to 1 MUX.

CSI-2111 Structure of Computers Ipage 5-13 Synthesis with too small MUX  Example: f(A,B,C)=  m (2, 3, 5, 6) 4-to-1 MUX f C A B {

CSI-2111 Structure of Computers Ipage 5-14 Synthesis with too small MUX *  Example: f(A,B,C)=  m (2, 3, 5, 6) 4-to-1 MUX f A B { f AB f 0 1 C C’ 0 1 C

CSI-2111 Structure of Computers Ipage 5-15 Synthesis with too small MUX *  f(A,B,C,D) =  m (0, 4, 5, 9, 13, 14, 15)  3 solutions, according to what is required: D 0 D 1 D’ to-1 MUX f ABC A’ 1 A A A to-1 MUX f BCD 4-to-1 MUX f AB C’D’ C C’D C+D

CSI-2111 Structure of Computers Ipage 5-16 Complex Multiplexers  It is possible to design multiplexers much more complex for particular uses: –Multiplexers of more than one bits –Multiple multiplexers –Multiplexers designed using smaller multiplexers (economy?)

CSI-2111 Structure of Computers Ipage 5-17 Demultiplexers  It distributes the bit E (or the word) to one of the 2 n possible destinations (specified by S). DEMUX 1 to 4 E D1D1 E D0D0 D2D2 D3D S1S S0S0

CSI-2111 Structure of Computers Ipage Three technologies of programmable logic Fixed AND array (decoder) Programmable OR array Programmable OR array InputsOutputs Connections programmable a) (Programmable) Read-Only Memory — (P)ROM Programmable AND array Fixed OR array InputsOutputs b) Programmable Array Logic (PAL) Connections programmable Programmable AND array Programmable OR array InputsOutputs Connections programmable c) Programmable Logic Array (PLA) Connected programmable

CSI-2111 Structure of Computers Ipage 5-19 ROM (Read-Only Memory)  Circuit made up of a matrix of register- memory for storing a fixed length information permanently. ROM 2 registers k of bitsn k inputs n outputs (adresses) (data)

CSI-2111 Structure of Computers Ipage 5-20 Synthesis with ROM  Any set of boolean functions f 1 (x 1, x 2 …, x k ) … f n (x 1, x 2 …, x k ) can be implemented using (2 k  n ) ROM and one level of programming.  Example: f 1 (I 1, I 0 ) =  m (1, 2, 3), f 2 (I 1, I 0 ) =  m (0, 2), 4x2 ROM 2x4 decoder I1I1 I0I f1f1 f2f2

CSI-2111 Structure of Computers Ipage 5-21 Synthesis with ROM *  Alternative representation of the solution: = fuse intact f 1 (I 1, I 0 ) =  m (0, 3) f 2 (I 1, I 0 ) = ( I 1 + I 0 )' f 3 (I 1, I 0 ) =  M (1) – The OR gates have all 4 entries nevertheless! Decoder 2 x I1I1 I0I f1f1 f2f2 f3f3

CSI-2111 Structure of Computers Ipage PLA (Programmable Logic Arrays)  Programmable logic arrays are made of:  One layer of product terms (AND gates)  One layer of sum terms (OR gates)  Three layers with inverter/fuses  Fuses in each layer are programmed k product terms (AND gates) m sum terms (OR gates) k x m fuses n x k fuses n inputs n x k fuses m fuses m outputs n inverters m inverters

CSI-2111 Structure of Computers Ipage 5-23 Synthesis with PLA *  Example  F 1 (A,B,C) =  m(3, 5, 6, 7)  F 2 (A,B,C) =  m(0, 2, 4)  Which are the terms produced of F 1, F 2, F 1 ’ and F 2 ’ ? F 1 (A,B,C) = AB + AC + BC F 1 & F 2 = 5 terms F 1 ’ (A,B,C) = A’B’ + A’C’+ B’C’ F 1 & F 2 ’ = 4 terms F 2 (A,B,C) = A’C’+ B’C’ F 1 ’ & F 2 = 3 terms F 2 ’ (A,B,C) = AB + C F 1 ’ & F 2 ’ = 5 terms

CSI-2111 Structure of Computers Ipage 5-24 Synthesis with PLA *  Example  F 1 (A,B,C) =  m(3, 5, 6, 7) = (A’B’ + A’C’+ B’C’)’  F 2 (A,B,C) =  m(0, 2, 4) = A’C’ + B’C’  The product terms are A’B’, A’C’ and B’C’ Programming 1 = used - = unused T = just as it is C = complementary 0 = complementary 1 = normal - = unused

CSI-2111 Structure of Computers Ipage 5-25 Synthesis with PLA *  Example  F 1 (A,B,C) =  m(3, 5, 6, 7) = (A’B’ + A’C’+ B’C’)’  F 2 (A,B,C) =  m(0, 2, 4) = A’C’ + B’C’  The product terms are A’B’, A’C’ and B’C’ Programming

CSI-2111 Structure of Computers Ipage 5-26 Synthesis with PLA * A B C CC’BB’AA’ A’B’ A’C’ B’C’ F2F2 F1’F1’ F2F2 F1F1

CSI-2111 Structure of Computers Ipage PAL (Programmable Array Logic)  Programmable logic networks made of:  One layer of product terms (AND gates)  One layer of sum terms (OR gates)  Programmable fuses with the 1st layer  More simplistic than the PLA, but less flexible k product terms (AND gates) m SUM terms (OR gates) n x k fuses n inputs n x k fuses m outputs n inverters

CSI-2111 Structure of Computers Ipage ALU (Arithmetic and Logic Unit) ArithmeticLogicShift DEMUX AB MUX F Control State (Status) ALU AB G C S AB G C S

CSI-2111 Structure of Computers Ipage 5-29 Shift/Rotation and Status Bits  Shift/rotation of a word of several bits via ALU.  Status bits updated by ALU – C : Carry – V : Overflow Indicator – Z :Zero – N :Negative value  Example: Z = ( F 0  F 1 ...  F n-1 ) AB F S XNZVC Logic of the conditions

CSI-2111 Structure of Computers Ipage 5-30 Complementary readings  In Mano and Kime: –Sections 3.1 to 3.5  Combinational circuits, except Logic Simulation (3.3) –Section 3.7  Multiplexers –Sections 6.6 to 6.9  Programmable logic, ROM, PLA, PAL –Sections 7.7 to 7.8  Arithmetic logic unit, shifter