Throughput of Internally Buffered Crossbar Switch Saturday, February 20, 2016 Mingjie Lin

Slides:



Advertisements
Similar presentations
1 Maintaining Packet Order in Two-Stage Switches Isaac Keslassy, Nick McKeown Stanford University.
Advertisements

Mobility Increase the Capacity of Ad-hoc Wireless Network Matthias Gossglauser / David Tse Infocom 2001.
1 Scheduling Crossbar Switches Who do we chose to traverse the switch in the next time slot? N N 11.
ATM Switch Architectures
CWI PNA2, Reading Seminar, Presented by Yoni Nazarathy EURANDOM and the Dept. of Mechanical Engineering, TU/e Eindhoven September 17, 2009 An Assortment.
Discrete Time Markov Chains
Markov Chains Ali Jalali. Basic Definitions Assume s as states and s as happened states. For a 3 state Markov model, we construct a transition matrix.
Submitters: Erez Rokah Erez Goldshide Supervisor: Yossi Kanizo.
Nick McKeown CS244 Lecture 6 Packet Switches. What you said The very premise of the paper was a bit of an eye- opener for me, for previously I had never.
Frame-Aggregated Concurrent Matching Switch Bill Lin (University of California, San Diego) Isaac Keslassy (Technion, Israel)
Isaac Keslassy, Shang-Tse (Da) Chuang, Nick McKeown Stanford University The Load-Balanced Router.
Algorithm Orals Algorithm Qualifying Examination Orals Achieving 100% Throughput in IQ/CIOQ Switches using Maximum Size and Maximal Matching Algorithms.
Performance analysis for high speed switches Lecture 6.
Fast Matching Algorithms for Repetitive Optimization Sanjay Shakkottai, UT Austin Joint work with Supratim Deb (Bell Labs) and Devavrat Shah (MIT)
1 Input Queued Switches: Cell Switching vs. Packet Switching Abtin Keshavarzian Joint work with Yashar Ganjali, Devavrat Shah Stanford University.
1 Performance Results The following are some graphical performance results out of the literature for different ATM switch designs and configurations For.
Crossbar Switches Crossbar switches are an important general architecture for fast switches. 2 x 2 Crossbar Switches A general N x N crossbar switch.
April 10, HOL Blocking analysis based on: Broadband Integrated Networks by Mischa Schwartz.
The Concurrent Matching Switch Architecture Bill Lin (University of California, San Diego) Isaac Keslassy (Technion, Israel)
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Input-Queued.
1 ENTS689L: Packet Processing and Switching Buffer-less Switch Fabric Architectures Buffer-less Switch Fabric Architectures Vahid Tabatabaee Fall 2006.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion MSM.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion The.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Scaling.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Statistical.
The Crosspoint Queued Switch Yossi Kanizo (Technion, Israel) Joint work with Isaac Keslassy (Technion, Israel) and David Hay (Politecnico di Torino, Italy)
1 EE384Y: Packet Switch Architectures Part II Load-balanced Switches Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University.
Maximum Size Matchings & Input Queued Switches Sundar Iyer, Nick McKeown High Performance Networking Group, Stanford University,
1 Achieving 100% throughput Where we are in the course… 1. Switch model 2. Uniform traffic  Technique: Uniform schedule (easy) 3. Non-uniform traffic,
Analysis of Input Queueing More complex system to analyze than output queueing case. In order to analyze it, we make a simplifying assumption of "heavy.
048866: Packet Switch Architectures Dr. Isaac Keslassy Electrical Engineering, Technion Scheduling.
Distributed Scheduling Algorithms for Switching Systems Shunyuan Ye, Yanming Shen, Shivendra Panwar
Previously, we learned that adding two numbers together which have the same absolute value but are opposite in sign results in a value of zero. This can.
1 Scheduling Crossbar Switches Who do we chose to traverse the switch in the next time slot? N N 11.
Pipelined Two Step Iterative Matching Algorithms for CIOQ Crossbar Switches Deng Pan and Yuanyuan Yang State University of New York, Stony Brook.
Localized Asynchronous Packet Scheduling for Buffered Crossbar Switches Deng Pan and Yuanyuan Yang State University of New York Stony Brook.
First Order Linear Equations Integrating Factors.
April 10, HOL Blocking analysis based on: Broadband Integrated Networks by Mischa Schwartz.
Lesson 9: Advanced M/G/1 Methods and Examples Giovanni Giambene Queuing Theory and Telecommunications: Networks and Applications 2nd edition, Springer.
13.7 – Graphing Linear Inequalities Are the ordered pairs a solution to the problem?
ATM SWITCHING. SWITCHING A Switch is a network element that transfer packet from Input port to output port. A Switch is a network element that transfer.
1 Copyright © Monash University ATM Switch Design Philip Branch Centre for Telecommunications and Information Engineering (CTIE) Monash University
Time Parallel Simulations II ATM Multiplexers and G/G/1 Queues.
Propagation Delay and Receiver Collision Analysis in WDMA Protocols I.E. Pountourakis, P.A. Baziana and G. Panagiotopoulos School of Electrical and Computer.
Author : Jing Lin, Xiaola Lin, Liang Tang Publish Journal of parallel and Distributed Computing MAKING-A-STOP: A NEW BUFFERLESS ROUTING ALGORITHM FOR ON-CHIP.
Network Design and Analysis-----Wang Wenjie Queueing System IV: 1 © Graduate University, Chinese academy of Sciences. Network Design and Analysis Wang.
1 IK1500 Communication Systems IK1500 Anders Västberg
Routers. These high-end, carrier-grade 7600 models process up to 30 million packets per second (pps).
ISLIP Switch Scheduler Ali Mohammad Zareh Bidoki April 2002.
Packet Forwarding. A router has several input/output lines. From an input line, it receives a packet. It will check the header of the packet to determine.
Abtin Keshavarzian Yashar Ganjali Department of Electrical Engineering Stanford University June 5, 2002 Cell Switching vs. Packet Switching EE384Y: Packet.
Stress Resistant Scheduling Algorithms for CIOQ Switches Prashanth Pappu Applied Research Laboratory Washington University in St Louis “Stress Resistant.
1 Markov chains and processes: motivations Random walk One-dimensional walk You can only move one step right or left every time unit Two-dimensional walk.
Based on An Engineering Approach to Computer Networking/ Keshav
Buffered Crossbars With Performance Guarantees Shang-Tse (Da) Chuang Cisco Systems EE384Y Thursday, April 27, 2006.
SNRC Meeting June 7 th, Crossbar Switch Scheduling Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University
1 Buffering Strategies in ATM Switches Carey Williamson Department of Computer Science University of Calgary.
Reduced Rate Switching in Optical Routers using Prediction Ritesh K. Madan, Yang Jiao EE384Y Course Project.
Virtual-Channel Flow Control William J. Dally
Input buffered switches (1)
scheduling for local-area networks”
Chapter 8 Switching Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Packet Forwarding.
Addressing: Router Design
DTMC Applications Ranking Web Pages & Slotted ALOHA
Packet Switching (basics)
Memory Management Algorithms Huan Liu, Damon Mosk-Aoyama
September 1, 2010 Dr. Itamar Arel College of Engineering
Scheduling Crossbar Switches
EE384Y: Packet Switch Architectures II
Presentation transcript:

Throughput of Internally Buffered Crossbar Switch Saturday, February 20, 2016 Mingjie Lin

2 Contents 1. Motivation  High throughput performance crossbar switch  What is the impact of crosspoint buffer on throughput of crossbar switch? 2. Problem Statement and Notations  The structure of a internally buffered crossbar switch (IBCS)  Two cases: 1. With blocking, 2. Without blocking  Markov Chain model 3. Analysis approach 4. Results summary

3 Background Switching Fabric IQOQ CQ

4 Motivations Classic results: ~58.3%(blocking) and ~63%(non-blocking) throughput for IQ crossbar switch

5 Motivations What will happen to the throughput if we add Crosspoint buffer?

6 Contents 1. Motivation  High throughput performance crossbar switch  What is the impact of crosspoint buffer on throughput of crossbar switch? 2. Problem Statement and Notations  The structure of a internally buffered crossbar switch (IBCS)  Two cases: 1. With blocking, 2. Without blocking  Markov Chain model 3. Analysis approach 4. Results summary

7 The structure of an internally buffered crossbar switch (IBCS) Input Traffic: i.i.d uniform Bernoulli type, independent at each input. Scheduling Algorithm (2 phases in 1 time slot): 1. Buffer In Phase: For each input queue i, each HOL packet goes to its destined crosspoint buffer cell if it is vacant. 2. Buffer Out Phase: For each output port j, randomly pick one cell from all occupied crosspoint buffer cells, and output its packet.

8 Throughput Analysis 2 Cases: 1. Non-Blocking Mode 2. Blocking Mode

9 Throughput Analysis 2 Cases: 1. Non-Blocking Mode 2. Blocking Mode Idea:  Using Markov Chain to model the crossbar switch behavior.

10 Notation Internal buffer cell; Input queue at input port I; For any column of buffer cells, the probability of having k packets in total at time n; state transition probability of Markov chain model.

11 Contents 1. Motivation  High throughput performance crossbar switch  What is the impact of crosspoint buffer on throughput of crossbar switch? 2. Problem Statement and Notations  The structure of a internally buffered crossbar switch (IBCS)  Two cases: 1. With blocking, 2. Without blocking  Markov Chain model 3. Analysis approach 4. Results summary

12 Observation 1. Symmetry: a) traffic b) switching fabric structure

13 Observation 1. Symmetry: a) traffic b) switching fabric structure 2. During each time slot, if there is at least 1 packet in B *,j, then there will be a packet to output

14 Observation 1. Symmetry: a) traffic b) switching fabric structure 2. During each time slot, if there is at least 1 packet in B *,j, then there will be a packet to output 3. Saturation Throughput:

15 Markov Chain

16 Derivation

17 Key Equation Total probability:

18 Key Equation Total probability:

19 Key Equation (cont.) N linear equations:

20 IBCS without blocking Solution of transition probability:

21 IBCS without blocking (cont.) Solve those N linear equations, we can compute through for any N.

22 IBCS without blocking (cont.) Solve those N linear equations, we can compute through for any N. Question: what happens to throughput if N goes to infinity?

23 IBCS without blocking (cont.) We know:

24 IBCS without blocking (cont.) We know: when

25 IBCS without blocking (cont.) Therefore:

26 IBCS without blocking (cont.) Add them up: finally:

27 IBCS without blocking (cont.) Which leads to:

28 IBCS with blocking Markov chain model, however, state space too large to manage

29 IBCS with blocking Markov chain model, however, state space too large to manage What is key difference between “with blocking” and “without blocking”?

30 IBCS with blocking Markov chain model, however, state space too large to manage What is key difference between “with blocking” and “without blocking”? What is thoughput if N goes to infinity?

31 IBCS with blocking (cont.)

32 IBCS with blocking (cont.)

33 IBCS with blocking (cont.) when Therefore: finally:

34 Contents 1. Motivation  High throughput performance crossbar switch  What is the impact of crosspoint buffer on throughput of crossbar switch? 2. Problem Statement and Notations  The structure of a internally buffered crossbar switch (IBCS)  Two cases: 1. With blocking, 2. Without blocking  Markov Chain model 3. Analysis approach 4. Results summary

35 Results Summary

36 Results Summary (cont.)

37 Results Summary (cont.) 1. Crosspoint buffer cells have a significant impact on throughput of crossbar switch Symmetry.

38 Results Summary (cont.) 1. Crosspoint buffer cells have a significant impact on throughput of crossbar switch Symmetry. 2. Without crosspoint buffer, throughput will decrease while N increases, the opposite is true for ICBS.

39 Results Summary (cont.) 1. Crosspoint buffer cells have a significant impact on throughput of crossbar switch Symmetry. 2. Without crosspoint buffer, throughput will decrease while N increases, the opposite is true for ICBS. 3. When N goes infinity, throughput of crossbar switch without crosspoint buffer will converge to ~63% without HOL blocking, but ICBS’s will converge to 100%.

40 Results Summary (cont.) 1. Crosspoint buffer cells have a significant impact on throughput of crossbar switch Symmetry. 2. Without crosspoint buffer, throughput will decrease while N increases, the opposite is true for ICBS. 3. When N goes infinity, throughput of crossbar switch without crosspoint buffer will converge to ~63% without HOL blocking, but ICBS’s will converge to 100%. 4. When N goes infinity, throughput of crossbar switch without crosspoint buffer will converge to ~58% without HOL blocking, but ICBS’s will converge to 100%.

41 Thank you!