“Self-Resetting Stage Logic” Presented by : Vishal Jain, ID: 200411029 Guided By: Prof. Anutosh Maitra.

Slides:



Advertisements
Similar presentations
Self-Timed Logic Timing complexity growing in digital design -Wiring delays can dominate timing analysis (increasing interdependence between logical and.
Advertisements

Chapter 4: Combinational Logic
Programmable FIR Filter Design
Multi-cellular paradigm The molecular level can support self- replication (and self- repair). But we also need cells that can be designed to fit the specific.
Dr. Rabie A. Ramadan Al-Azhar University Lecture 3
1/1/ /e/e eindhoven university of technology Microprocessor Design Course 5Z008 Dr.ir. A.C. (Ad) Verschueren Eindhoven University of Technology Section.
Chapter 8. Pipelining. Instruction Hazards Overview Whenever the stream of instructions supplied by the instruction fetch unit is interrupted, the pipeline.
FPGA-Based System Design: Chapter 6 Copyright  2004 Prentice Hall PTR Register-transfer Design n Basics of register-transfer design: –data paths and controllers.
Digital Integrated Circuits© Prentice Hall 1995 Timing ISSUES IN TIMING.
Applications of Systolic Array FTR, IIR filtering, and 1-D convolution. 2-D convolution and correlation. Discrete Furier transform Interpolation 1-D and.
COMP Clockless Logic and Silicon Compilers Lecture 3
Recap – Our First Computer WR System Bus 8 ALU Carry output A B S C OUT F 8 8 To registers’ input/output and clock inputs Sequence of control signal combinations.
1 Atanasoff–Berry Computer, built by Professor John Vincent Atanasoff and grad student Clifford Berry in the basement of the physics building at Iowa State.
Pipelining By Toan Nguyen.
Lecture # 12 University of Tehran
Basic Processing Unit (Week 6)
EE345: Introduction to Microcontrollers Register and Counters Prof. Ahmad Abu-El-Haija.
Registers and Counters
Advanced FPGA Based System Design Lecture-9 & 10 VHDL Sequential Code By: Dr Imtiaz Hussain 1.
Bus Architecture Memory unit AR PC DR E ALU AC INPR 16-bit Bus IR TR
Rabie A. Ramadan Lecture 3
Finite State Machines (FSMs) and RAMs and inner workings of CPUs COS 116, Spring 2010 Guest: Szymon Rusinkiewicz.
COSC 3430 L08 Basic MIPS Architecture.1 COSC 3430 Computer Architecture Lecture 08 Processors Single cycle Datapath PH 3: Sections
1 Presented By Şahin DELİPINAR Simon Moore,Peter Robinson,Steve Wilcox Computer Labaratory,University Of Cambridge December 15, 1995 Rotary Pipeline Processors.
Lecture 8: Processors, Introduction EEN 312: Processors: Hardware, Software, and Interfacing Department of Electrical and Computer Engineering Spring 2014,
Lecture 14: Processors CS 2011 Fall 2014, Dr. Rozier.
Important Components, Blocks and Methodologies. To remember 1.EXORS 2.Counters and Generalized Counters 3.State Machines (Moore, Mealy, Rabin-Scott) 4.Controllers.
Speeding up of pipeline segments © Fr Dr Jaison Mulerikkal CMI.
Parallel architecture Technique. Pipelining Processor Pipelining is a technique of decomposing a sequential process into sub-processes, with each sub-process.
Introduction to State Machine
Lecture 13: Logic Emulation October 25, 2004 ECE 697F Reconfigurable Computing Lecture 13 Logic Emulation.
ECE 456 Computer Architecture Lecture #14 – CPU (III) Instruction Cycle & Pipelining Instructor: Dr. Honggang Wang Fall 2013.
SEQUENTIAL LOGIC By Tom Fitch. Types of Circuits Combinational: Gates Combinational: Gates Sequential: Flip-Flops Sequential: Flip-Flops.
Principles of Linear Pipelining
VLIW Digital Signal Processor Michael Chang. Alison Chen. Candace Hobson. Bill Hodges.
Principles of Linear Pipelining. In pipelining, we divide a task into set of subtasks. The precedence relation of a set of subtasks {T 1, T 2,…, T k }
Chapter One Introduction to Pipelined Processors
Lecture 21: Registers and Counters (1)
Computer Organization CDA 3103 Dr. Hassan Foroosh Dept. of Computer Science UCF © Copyright Hassan Foroosh 2002.
CSE115: Introduction to Computer Science I Dr. Carl Alphonce 219 Bell Hall
How Computers Work Lecture 12 Page 1 How Computers Work Lecture 12 Introduction to Pipelining.
Pipelined and Parallel Computing Partition for 1 Hongtao Du AICIP Research Nov 3, 2005.
LECTURE 4 Logic Design. LOGIC DESIGN We already know that the language of the machine is binary – that is, sequences of 1’s and 0’s. But why is this?
Chapter One Introduction to Pipelined Processors
Principles of Linear Pipelining
EE3A1 Computer Hardware and Digital Design Lecture 9 Pipelining.
1 Neutron Monitor Workshop 2(A): Principles of Digital Logic Mahidol University June 25, 2009 Paul Evenson University of Delaware Bartol Research Institute.
1 Recap: Lecture 4 Logic Implementation Styles:  Static CMOS logic  Dynamic logic, or “domino” logic  Transmission gates, or “pass-transistor” logic.
Chapter One Introduction to Pipelined Processors.
LECTURE 5: CPU and MEMORY. electronic components I. Four main types of electronic components in computers: 1. transistors/resistors 1. transistors/resistors.
Clockless Chips Under the esteemed guidance of Romy Sinha Lecturer, REC Bhalki Presented by: Lokesh S. Woldoddy 3RB05CS122 Date:11 April 2009.
Mu.com.lec 11.  Used not only to perform addition but also to perform subtraction, multiplication and division  The most basic of the adders is the.
Gandhinagar Institute of Technology
Computer Orgnization Rabie A. Ramadan Lecture 9. Cache Mapping Schemes.
Controller Implementation
Control Unit Operation
Welcome To Seminar Presentation Seminar Report On Clockless Chips
Sequential Circuit: Counter
Chapter One Introduction to Pipelined Processors
CHAPTER 2 Testing Throughout the Software Life Cycle
Pipelining Example Cycle 1 b[0] b[1] b[2] + +
CSE Winter 2001 – Arithmetic Unit - 1
Serial versus Pipelined Execution
CSE 370 – Winter Sequential Logic-2 - 1
Registers.
Guest Lecture by David Johnston
Pipelining: Basic Concepts
Digital Electronics and Logic Circuit
Pipelining.
Pipelining and Superscalar Techniques
Presentation transcript:

“Self-Resetting Stage Logic” Presented by : Vishal Jain, ID: Guided By: Prof. Anutosh Maitra

What is SRSL? 1.Synchronization approach 2.Data flow 3.clock less designs 4.Uses single rail encoding. Why new thing? SRSL is a simple, efficient and easy to implement therefore it is acceptable.

What has been implemented and what is going on in SRSL? >16 stage four bit linear pipe (April,2004 by Abdel Ejnioui, University of Central Florida) > RAM cell design had been tested successfully > Trying to implement for larger network.

2. Basic Circuit – 1 Bit 1. Introduction 3. Basic Circuit – Multi Bits 4. Pipeline : Linear 4-Stages 6. Analysis 5. Nonlinear : Fork and Join Contents: 7. SRSL in Multiagent Model

Introduction Self Resetting stage logic: A pipeline stage resets itself before starting a new execution cycle. Two Phases 1.Evaluation Phase : when it executes the instruction and output is result of evaluation of its input 2.Reset Phase : When output is Null Data flow Evaluate phase Reset phase

2. SRSL for ONE BIT Every Long journey starts with Small Step

1

1

1

1

1

1 0

00

00

1

3. Extending SRSL for multi bits One and one makes eleven

4. Linear Pipelining with SRSL Let us do some more interesting thing

Principle of Linear Pipelining Let T be a task which can be partitioned Into k subtasks (aka stages)according to linear precedence Relation: T={T 1,T 2,…,T k }; A subtask T j can not start until {T i  i<j} are Finished.This can be modeled with the linear precedence graph: T2T2 T1T1 TkTk

Can you help me if I am a pipeline with Fork and Join ? 5. Fork and Join operations in pipeline

Fork and Join of DATA streams: 1.Fork : 2. Join : A B F E D C

6. Analysis of Linear Pipeline

Notations: d( E n ) = time of Execution phase of n th stage d( R n ) = time of Reset phase of n th stage P n = time of Stage n Observations because of Invert-And delay 1.d(E n )=d(R n )=P n /2 2.d(R n-1 ) < d(R n ) 3.d(E n-1 ) > d(E n )

What we observe from graph?? We can’t go beyond a certain limit of cascading because evaluation reset phase time decreases and here comes limitation of SRSL. Therefore it is not Scalable in present scenario.

7. How SRSL may be benificial for Multiagent Model?

Noval Idea: I suggest use this mechanism to implement Data Join in “Hierarchical Multiagent Model” and present possible advantages by using this model in hierarchical Multiagent Model: a b c d e The key ideas behind the SRMM are 1.“Whenever Data is ready it is delivered to the higher level Agent. Without any signaling protocol which saves time.” 2.“The Higher level agent always get latest data.”

References: 1.G.Jung, V.Sudharajan and G.E. Sobelman “ A self resetting 32-bit parallel adder”. 2.“Parallelism Scalability and Programmability” Kai Hwang 3.“Multistage Modeling” search results of Google.com 4.Lecture Notes, Prof. Anutosh Maitra

Thanking You