Implementation of Turbo Code in TI TMS320C8x Hao Chen Instructor: Prof. Yu Hen Hu ECE734 Spring 2004

Turbo Codes Shannon established the fundamental theory about the transmission rates in digital communication system The practically feasible channel utilization is almost closed to the theory communication capacity limit; The lower complexity of decoder is gained through two separately decoder compared with one decode; Turbo Codes play an important role in the next generation communication system

Encoder of Turbo Code Parallel concatenation convolutional codes (PCCC) Output sequence has near uniform distribution probability with well designed interleaver.

Convolutional (RSC) Encoder Generator matrix of a rate ½ RSC code can be defined:

Viterbi Algorithm for Convolutional Code P(i,t) : The min cost when the state is i at the time t. S(i, t): The path from time 1 to t corresponding to the P(i,t).

A Posteriori Probability Algorithm (APP) Minimize the symbol error probability The code is decided by the log-likelihood ratio Original infromation at time t : The received sequence from time 1 to time T

Iterative algorithm of Turbo Code Two component decoders serially concatenated via an interleaver The priori probabilities obtained from first decoder is used at the second decoder

Iterative algorithm of Turbo Code Use priori information to caculate Forward recursion: t=1, 2, …, T Backward recursion: t=T, T-1, …, 2, 1 log-likelihood ratio

Implementation in TMS320C8x Modify the algorithm to save memory Apply two decoders in one DSP; (time share) Map the algorithm to utility multiprocessor of TMS320C8x more efficiently;

Memory location analysis Step 1: Receive the code sequence; get the for decoder1.

Memory location analysis Step 4: Calcualte of decoder 1 with

Implement forward recursion Map forward recursion to four parallel processors of TMS320C8x No additional memory is needed to store temporary value