Lecture 8 Review Combinational Devices –Decoder –Multiplexor (Bhasker p-81) –Shifter –Barrel Shifter (Bhasker p-303)

Slides:

Advertisements

Similar presentations

Multiplexers Section 3-7 Mano & Kime. Multiplexers & Demultiplexers Multiplexers (Selectors) Lab 1 – Behavioral VHDL -- Multiplexers MUX as a Universal.

Advertisements

Quad 2-to-1 and Quad 4-to-1 Multiplexers Discussion D2.4 Example 7.

Decoders Discussion D9.5 Example 25. Decoders 3-to-8 Decoder decoder38.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all;

Arithmetic Logic Unit (ALU)

1 VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi.

Shifters Discussion D7.1 Example Bit Shifter.

Divider Discussion D7.3 Example 20.

Generic Multiplexers: Parameters Discussion D2.5 Example 8.

2-to-1 Multiplexer: if Statement Discussion D2.1 Example 4.

Decoders and Encoders Lecture L4.2. Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders.

Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.

FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.

Introduction to VHDL Multiplexers. Introduction to VHDL VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.

4-to-1 Multiplexer: case Statement Discussion D2.3 Example 6.

Logic Design Fundamentals - 2 Lecture L1.2. Logic Design Fundamentals - 2 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.

Decoders and Encoders Sections 3-5, 3-6 Mano & Kime.

Introduction to VHDL Multiplexers Discussion D1.1.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.

1 Part II: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

Binary-to-BCD Converter

Binary-to-BCD Converter

4-bit Shift Register. 2-bit Register Serial-in-serial-out Shift Register.

1 Part V: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

ECE 448: Spring 12 Lab Midterm Exam Review. Part 1: Detailed discussion of a selected midterm from Spring Part 2: Review & discussion of common.

Binary-to-BCD Converter

A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body. Four types of concurrent assignment statements –Simple.

1 Part I: SYSTEM DESIGN. 2 Packages and Components Functions and Procedures Problem (Design & Implementation) Additional System Designs.

ELEC / Computer Architecture and Design Fall 2009 ELEC / Computer Architecture and Design Fall 2009 Modeling for Synthesis.

Shannon decomposition William Sandqvist Claude Shannon mathematician / electrical engineer (1916 –2001) William Sandqvist

VHDL for Combinational Circuits. VHDL We Know Simple assignment statements –f

1 ECE 545 – Introduction to VHDL Dataflow Modeling of Combinational Logic Simple Testbenches ECE 656. Lecture 2.

Mixed Style RTL Modeling

ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

2’s Complement 4-Bit Saturator Discussion D2.8 Lab 2.

4-to-1 Multiplexer: Module Instantiation Discussion D2.2 Example 5.

16/11/2006DSD,USIT,GGSIPU1 Packages The primary purpose of a package is to encapsulate elements that can be shared (globally) among two or more design.

Digital System Projects

1 Part III: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

9/9/2006DSD,USIT,GGSIPU1 Concurrent vs Sequential Combinational vs Sequential logic –Combinational logic is that in which the output of the circuit depends.

CS/EE 3700 : Fundamentals of Digital System Design

04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)

George Mason University ECE 448 – FPGA and ASIC Design with VHDL VHDL Coding for Synthesis ECE 448 Lecture 12.

ECE 448 – FPGA and ASIC Design with VHDL George Mason University ECE 448 Lab 1 Implementing Combinational Logic in VHDL.

EGRE 6311 LHO 04 - Subprograms, Packages, and Libraries EGRE 631 1/26/09.

Fundamentals of Digital Signal Processing יהודה אפק, נתן אינטרטור אוניברסיטת תל אביב.

1 Introduction to Engineering Spring 2007 Lecture 19: Digital Tools 3.

Combinational logic circuit

Describing Combinational Logic Using Processes

UNIT 8: Synthesis Basics

Part IV: VHDL CODING.

Combinational Circuits Using VHDL

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

BARREL SHIFTER.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

Mano and Kime Sections 7-6 – 7-8

ECE-C 302 Lecture 15 Prawat Nagvajara

Binary-to-BCD Converter

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

Data Flow Modeling of Combinational Logic

Concurrent vs Sequential

Modeling of Circuits with a Regular Structure

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

ECE 331 – Digital System Design

Data Flow Description of Combinational-Circuit Building Blocks

Data Flow Description of Combinational-Circuit Building Blocks

Modeling of Circuits with a Regular Structure

Modeling of Circuits with Regular Structure

4-Input Gates VHDL for Loops

디 지 털 시 스 템 설 계 UP2 Kit를 이용한 카운터 설계

Presentation transcript:

Lecture 8 Review Combinational Devices –Decoder –Multiplexor (Bhasker p-81) –Shifter –Barrel Shifter (Bhasker p-303)

Decoder DEC N inputs 2**N outputs Z(0), …, Z(2**N-1) En Outputs are Zero’s when en=‘0’ X: N-bit vector input or an unsigned integer Only the xth output is a ‘1’ others are ‘0’

Decode Code Package dec_pack is constant N: integer := 16; subtype my_input integer range 0 to 2**N-1; End dec_pack; -- compile dec_pack into work library Library ieee; Use work.dec_pack.all; ieee.std_logic_1164.all Entity decoder is Port(x: in my_input; z: out std_logic_vector(0 to (2**N)-1); End decoder;

Decoder Architecture behav of decoder is begin Process(x) Begin If en = ‘1’ then for i in 0 to n-1 loop if i = x then z(i) <= ‘1’; else z(i) <= ‘0’; end if; end loop; End if; End process; End behav;

A 4-to-1 Mux Code Process(a,b,c,d,ctrl) Variable temp: std_logic; Begin case ctrl is when “00” => temp := a; when “01” => temp := b; when “10” => temp := c; when “11” => temp := d; when others => temp := ‘x’; end case; Z <= temp after mux_delay; End process;

Shifter Combinational logic, i.e., not a storage Routing switch Entity my_shifter is Generic(N : natural := 32); Port( x : in std_logic_vector(0 to n-1); sel: in std_logic_vector(0 to 2); z : out std_logic_vector(0 to n-1)); End my_shifter; -- sel: “000” no shift, “001” shift right, --“010” shift left, “011” rotate right, --“100” rotate left, others not used.

Barrel Shifter -- Rotate left by a specified number Entity Barrel_shifter is generic(N: positive := 4); port( DATA: in std_logic_vecter(n-1 downto 0); selekt: in integer range 0 to N-1; b_out: out std_logic_vecter(n-1 downto 0)); End barrel_shifter; Architecture concurrent_statement of barrel_shifter is Begin b_out 0 else DATA; End concurrent_statement;