Vienna Group Discussion Meeting on Luminosity CERN, 9 May 2006 Presented by Claudia-Elisabeth Wulz Luminosity and the Global Trigger A. Taurok, I. Magrans de Abril, C.-E. Wulz

Luminosity Meeting, May 2006 C. - E. Wulz2 Global Trigger Crate PSB (Pipelined Synchronizing Buffer) Input and Synchronisation GMT (Global Muon Trigger) Global Muon Trigger logic GTL (Global Trigger Logic) Algorithm logic FDL (Final Decision Logic) Level-1 Accept decision GTFE (Global Trigger Frontend) Readout TCS (Trigger Control System Module) Central Trigger Control L1A_OUT (Level-1 Accept Module) Distribution of Level-1 Accept CONV6U (Conversion Boards) Reception of status signals from the subsystems TIM (Timing Module) Timing

Luminosity Meeting, May 2006 C. - E. Wulz3 Final Decision Logic (FDL) Board

Luminosity Meeting, May 2006 C. - E. Wulz4 FDL functionality The Final Decision Logic (FDL) board receives 128 algorithm bits from the Global Trigger Logic (GTL) board and 64 Technical Trigger bits from a dedicated Pipeline Synchronizing Buffer input board (PSB0). 8 Final OR’s are available (only 1 in normal running). A mask (also a veto mask for technical triggers if required) is applied to the algorithm bits to determine the Final OR’s. The Final OR’s go to the Trigger Control System (TCS) board, which delivers the L1A signals to the front-end electronics through two L1AOUT boards.

Luminosity Meeting, May 2006 C. - E. Wulz5 FDL block diagram Rate counters monitor each trigger algorithm bit and prescalers downscale the average rate if required (maximum reduction factor 2 16 = 65536, down to 600 Hz). Each algo and technical trigger bit first goes to the corresponding prescaler. Each prescaled trigger bit then goes to a rate counter and the ring buffer for readout.

Luminosity Meeting, May 2006 C. - E. Wulz6 FDL Rate counters 128 rate counters for physics triggers 64 rate counters for technical triggers All these counters are currently 16-bit, which overflow after 0.6 s at 100 kHz. A mimimal number of 32-bit counters, which overflow after 11.9 h at 100 kHz, could be implemented for algorithms used for luminosity measurement. How many depends on space of the chip. TBD! Rate counters stop at ‘FFFF’. The update period of these counters is programmable (8 possible values from s to 10 5 s). Each time a counter is reset its value is moved to the RATE_COUNTER register, which can be read out through VME. The values will be stored in the Conditions Database, and should be accessible for monitoring from there.

Luminosity Meeting, May 2006 C. - E. Wulz7 L1AOUT, TCS

Luminosity Meeting, May 2006 C. - E. Wulz8 TCS functionality The central Trigger Control System (TCS) board controls instantaneous and average L1A rates according to: - trigger throttling rules - emulation of front-end buffers - status of subdetector partitions It generates fast commands (BCRes, L1Reset and other Bgo commands) to be distributed to the subdetectors by the TTC network. It generates calibration and test trigger sequences. It has several counters for monitoring purposes, including dead-time counters.

Luminosity Meeting, May 2006 C. - E. Wulz9 TCS block diagram

Luminosity Meeting, May 2006 C. - E. Wulz10 Monitoring and dead-time counters on TCS chip Counters in each of the 8 DAQ partitions: - Nr. of beam crossings (BC) where L1A was inhibited (dead-time counter for all BC). - Nr. of active (according to LHC BC structure) BC where L1A was inhibited (dead-time counter for active BC). - Nr. of BC where L1A was inhibited and L1A is true (lost triggers). - Nr. of distributed physics triggers (physics L1A with dead-time). - Orbit nr. (32-bit).

Luminosity Meeting, May 2006 C. - E. Wulz11 Monitoring and dead-time counters on TCS chip Counters existing only DAQ partition 0 (DAQ0): - Nr. of active BC where L1A was inhibited by private orbits. - Nr. of active BC where L1A was inhibited by subdetector partitions. - Nr. of active BC where L1A was inhibited by trigger throttling rules. - Nr. of active BC where L1A was inhibited by calibration or test cycles. - Nr. of physics triggers (physics L1A without dead-time). Note that FDL has counters for all Final OR’s and technical triggers. - Nr. of distributed calibration triggers. - Nr. of distributed random (test) triggers. - Nr. of missing BC (no beam). - Event number (total number of distributed L1A for all partitions, for EVM). Note that the requested dead-time counters for normal rate (all DAQ partitions) and throttled rate (only DAQ0 partition) are now available.

Luminosity Meeting, May 2006 C. - E. Wulz12 L1AOUT 2 LVDS signals on an Ethernet connector are available to gate luminosity counters: LUM1: Running (reset by start/stop) LUM2: Active time for L1A (OR of all dead-times, inverted)

Luminosity Meeting, May 2006 C. - E. Wulz13 Trigger Supervisor Monitoring and Conditions DB XDAQ executive FL1.xml XDAQ executive FL2.xml Monitor Collector FL1.xml Control Cell #1 (GT/TCS Leaf) FL1.xml Monitor Sensor XDAQ executive Control Cell #2 (Other subsystem Leaf) Monitor Sensor pull DataSource FL2.xml Cell (TS) Cell (#2) Cell (#1) Controller side TS client (Web page) L1-Trigger Conditions DB Luminosity DB Luminosity Server I. Magrans

Luminosity Meeting, May 2006 C. - E. Wulz14 Summary The FDL, TCS and L1AOUT boards are relevant for luminosity. Counters for measuring rates and dead-times are available on FDL and TCS boards. Counters can be accessed though VME for monitoring purposes. The luminosity monitoring will be integrated in the central monitoring, using the Conditions Database and the Trigger Supervisor.