Coding and Error Control Chapter 8

Coping with Data Transmission Errors Error detection codes Detects the presence of an error Automatic repeat request (ARQ) protocols Block of data with error is discarded Transmitter retransmits that block of data Error correction codes, or forward correction codes (FEC) Designed to detect and correct errors

Error Detection Probabilities Pb : Probability of single bit error (BER) P1 : Probability that a frame arrives with no bit errors P2 : Probability that a frame arrives with one or more errors F: frame length, number of bits per frame P1 ? P2 ?

Error Detection Probabilities With no error detection F = Number of bits per frame

Error Detection Probabilities The probability that a frame arrives with no bit errors (P1) decreases when the probability of a single bit error increases. The probability that a frame arrives with no bit errors (P1) decreases with increasing frame length; the longer the frame, the more bits it has and the higher the probability that one of these is in error.

Error Detection Process Transmitter For a given frame, an error-detecting code (check bits) is calculated from data bits Check bits are appended to data bits Receiver Separates incoming frame into data bits and check bits Calculates check bits from received data bits Compares calculated check bits against received check bits Detected error occurs if mismatch

Parity Check Simplest error detection scheme Parity bit appended to a block of data Even parity Added bit ensures an even number of 1s Odd parity Added bit ensures an odd number of 1s Example, 7-bit character [1110001] Even parity [11100010] Odd parity [11100011]

Parity Check Odd parity Receiver examines the received character and if the total number of 1 is odd, assumes no errors. If one bit is erroneously inverted during transmission then the receiver will detect an error if two (or any even number) of bits are inverted due to error, an undetected error occurs. The use of the parity bit is not foolproof, as noise impulses are often long enough to destroy more than one bit, particularly at high data rates.

Cyclic Redundancy Check (CRC) Transmitter For a k-bit block, transmitter generates an (n-k)-bit frame check sequence (FCS) Resulting frame of n bits is exactly divisible by predetermined number Receiver Divides incoming frame by predetermined number If no remainder, assumes no error

CRC using Modulo 2 Arithmetic Exclusive-OR (XOR) operation Parameters: T = n-bit frame to be transmitted D = k-bit block of data; the first k bits of T F = (n – k)-bit FCS; the last (n – k) bits of T P = pattern of n–k+1 bits; this is the predetermined divisor Q = Quotient R = Remainder

CRC using Modulo 2 Arithmetic For T/P to have no remainder, start with Divide 2n-kD by P gives quotient and remainder Use remainder as FCS

CRC using Modulo 2 Arithmetic Does R cause T/P have no remainder? Substituting, No remainder, so T is exactly divisible by P

Example

Example

CRC using Polynomials All values expressed as polynomials Dummy variable X with binary coefficients

CRC using Polynomials

CRC using Polynomials Widely used versions of P(X) CRC–12 CRC–16 X12 + X11 + X3 + X2 + X + 1 CRC–16 X16 + X15 + X2 + 1 CRC – CCITT X16 + X12 + X5 + 1 CRC – 32 X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

Wireless Transmission Errors Error detection requires retransmission Detection inadequate for wireless applications Error rate on wireless link can be high, results in a large number of retransmissions Long propagation delay compared to transmission time => Inefficient system Error correction is more suitable

Block Error Correction Codes Transmitter Forward error correction (FEC) encoder maps each k-bit block into an n-bit block codeword Codeword is transmitted; analog for wireless transmission During transmission, the signal is subject to noise, which may produce bit errors in the signal. Receiver Incoming signal is demodulated Block passed through an FEC decoder

Forward Error Correction Process

FEC Decoder Outcomes No errors present Codeword produced by decoder matches original codeword Decoder detects and corrects bit errors Decoder detects but cannot correct bit errors; reports uncorrectable error Decoder detects no bit errors, though errors are present, typically rare

Block Code Principles E.g., v1=011011; E.g., v2=110001; d(v1, v2)=3 Hamming distance – for 2 n-bit binary sequences, the number of different bits E.g., v1=011011; E.g., v2=110001; d(v1, v2)=3 Suppose we wish to transmit blocks of data of length k bits. Instead of transmitting each block as k bits, we map each k-bit sequence into a unique n-bit codeword.

Block Code Principles For k=2 and n=5 Received : 00100=> not a valid codeword=>error Can it be corrected? Give the distance between 00100 and each possible codeword !

Block Code Principles For k=2 and n=5 Received : 00100=> not a valid codeword=>error Can it be corrected? Notice that 1 bit change to transform the valid codeword 00000 into 00100 2 bits changes to transform 00111 into 00100 3 bits changes to transform 11110 to 00100 4 bits changes to transform 11001 into 00100 d(00000, 00100)=1; d(00111, 00100)=2; d(11110, 00100)=3; d(11001, 00100)=3 => Rule : For invalid codeword, choose the closest (minimum distance) valid codeword

Block Code Principles For a code consisting of the valid codewords w1 , w2 ,…, ws , the minimum distance dmin of the code is defined as: The maximum number of guaranteed correctable errors t The number of errors that can be detected is

Convolutional Codes Defined by 3 parameters (n, k, K) code Input processes k bits at a time Output produces n bits for every k input bits K = constraint factor k and n generally very small n-bit output of (n, k, K) code depends on: Current block of k input bits Previous K-1 blocks of k input bits Example; (n, k, K) = (2,1,3)??

Convolutional Encoder

Convolutional Codes (n, k, K) = (2,1,3) The initial state of the machine corresponds to the all-zeros state. For our example (Figure 8.9b) there are 4 states, one for each possible pair of values for the last two bits. The next input bit causes a transition and produces an output of two bits.

Convolutional Codes For example, if the last two bits were 10 (It-1= 1, It-2 = 0) and the next bit is 1 (It = 1), What is the current state ? What is the next state ? What is the output? O1 = It-2 XOR It-1 XOR It O2 = It-2 XOR It

Convolutional Codes For example, if the last two bits were 10 (It-1= 1, It-2 = 0) and the next bit is 1 (It = 1), current state is state b (10) and the next state is d (11). The output is O1 = It-2 XOR It-1 XOR It = 0 XOR 1 XOR 1 = 0 O2 = It-2 XOR It = 0 XOR 1 = 1

Decoding Trellis diagram – expanded encoder diagram Viterbi code – error correction algorithm Compares received sequence with all possible transmitted sequences Algorithm chooses path through trellis whose coded sequence differs from received sequence in the fewest number of places Once a valid path is selected as the correct path, the decoder can recover the input data bits from the output code bits

Error Control Mechanisms to detect and correct transmission errors Types of errors: Lost PDU : a PDU fails to arrive Damaged PDU : PDU arrives with errors

Automatic Repeat Request Mechanism used in data link control and transport protocols Relies on use of an error detection code (such as CRC) ARQ is closely related to Flow Control

Flow Control Why invented ? Differences in machine performance: A may send data to B much faster than B can receive. Or B may be shared by many processes and cannot consume data received at the rate that A sends. Data may be lost at B due to lack of buffer space – waste of resources ! What does it do ? Flow control prevents buffer overflow at receiver How does it work ? Sliding window Credits

Flow Control Assures that transmitting entity does not overwhelm a receiving entity with data Protocols with flow control mechanism allow multiple PDUs in transit at the same time PDUs arrive in same order they’re sent Sliding-window flow control Transmitter maintains list (window) of sequence numbers allowed to send Receiver maintains list allowed to receive

Flow Control flow control is the process of managing the rate of data transmission between two nodes In order to prevent a fast sender from outrunning a slow receiver. It provides a mechanism for the receiver to control the transmission speed, so that the receiving node is not overwhelmed with data from transmitting node. Flow control should be distinguished from congestion control, which is used for controlling the flow of data when congestion has actually occurred Flow control is important because it is possible for a sending computer to transmit information at a faster rate than the destination computer can receive and process it. This can happen if the receiving computers have a heavy traffic load in comparison to the sending computer, or if the receiving computer has less processing power than the sending computer.

On the example, packets are numbered 0, 1, 2, .. The sliding window principle works as follows: a window size W is defined. In this example it is fixed. In general, it may vary based on messages sent by the receiver. The sliding window principle requires that, at any time: number of unacknowledged packets at the receiver <= W the maximum send window, also called offered window is the set of packet numbers for packets that either have been sent but are not (yet) acknowledged or have not been sent but may be sent. the usable window is the set of packet numbers for packets that may be sent for the first time. The usable window is always contained in the maximum send window. the lower bound of the maximum send window is the smallest packet number that has been sent and not acknowledged the maximum window slides (moves to the right) if the acknowledgement for the packet with the lowest number in the window is received A sliding window protocol is a protocol that uses the sliding window principle. With a sliding window protocol, W is the maximum number of packets that the receiver needs to buffer in the re-sequencing (= receive) buffer.

The previous slide shows an example of ARQ protocol, which uses the following details: 1. window size = 4 packets; 2. Acknowledgements are positive and are cumulative, i.e. indicate the highest packet number up to which all packets were correctly received 3. Loss detection is by timeout at sender 4. When a loss is detected, the source starts retransmitting packets from the last acknowledged packet (this is called Go Back n). Q. Is it possible with this protocol that a packet is retransmitted whereas it was correctly received?

The previous slide shows an example of ARQ protocol, which uses the following details: 1. window size = 4 packets; 2. Acknowledgements are positive and are cumulative, i.e. indicate the highest packet number up to which all packets were correctly received 3. Loss detection is by timeout at sender 4. When a loss is detected, the source starts retransmitting packets from the last acknowledged packet (this is called Go Back n). Q. Is it possible with this protocol that a packet is retransmitted whereas it was correctly received? A. Yes, for several reasons 1. If an ack is lost 2. If packet n is lost and packet n+ 1 is not

An Example of ARQ Protocol with Go Back N and Negative Acks

The previous slide shows an example of ARQ protocol, which uses the following details: 1. window size = 4 packets; 2. Acknowledgements are positive or negative and are cumulative. A positive ack indicates that packet n was received as well as all packets before it. A negative ack indicates that all packets up to n were received but a packet after it was lost 3. Loss detection is either by timeout at sender or by reception of negative ack. 4. When a loss is detected, the source starts retransmitting packets from the last acknowldeged packet (Go Back n). Q. What is the benefit of this protocol compared to the previous? A. If the timer T1 cannot be set very accurately, the previous protocol may wait for a long time before detecting a loss. This protocol reacts more rapidly.

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Error Control Requirements Error detection Receiver detects errors and discards PDUs Positive acknowledgement Destination returns acknowledgment of received, error-free PDUs Retransmission after timeout Source retransmits unacknowledged PDU Negative acknowledgement and retransmission Destination returns negative acknowledgment to PDUs in error

Go-back-N ARQ Acknowledgments Contingencies RR = receive ready (no errors occur) REJ = reject (error detected) Contingencies Damaged PDU Damaged RR Damaged REJ

Appendix

Error Detection Process

CRC using Digital Logic Dividing circuit consisting of: XOR gates Up to n – k XOR gates Presence of a gate corresponds to the presence of a term in the divisor polynomial P(X) A shift register String of 1-bit storage devices Register contains n – k bits, equal to the length of the FCS

Digital Logic CRC

Error Detection Probabilities Definitions Pb : Probability of single bit error (BER) P1 : Probability that a frame arrives with no bit errors P2 : While using error detection, the probability that a frame arrives with one or more undetected errors P3 : While using error detection, the probability that a frame arrives with one or more detected bit errors but no undetected bit errors

Error Detection Probabilities With no error detection F = Number of bits per frame

Block Code Principles Hamming distance – for 2 n-bit binary sequences, the number of different bits E.g., v1=011011; v2=110001; d(v1, v2)=3 Redundancy – ratio of redundant bits to data bits Code rate – ratio of data bits to total bits Coding gain – the reduction in the required Eb/N0 to achieve a specified BER of an error-correcting coded system

Hamming Code Designed to correct single bit errors Family of (n, k) block error-correcting codes with parameters: Block length: n = 2m – 1 Number of data bits: k = 2m – m – 1 Number of check bits: n – k = m Minimum distance: dmin = 3 Single-error-correcting (SEC) code SEC double-error-detecting (SEC-DED) code

Hamming Code Process Encoding: k data bits + (n -k) check bits Decoding: compares received (n -k) bits with calculated (n -k) bits using XOR Resulting (n -k) bits called syndrome word Syndrome range is between 0 and 2(n-k)-1 Each bit of syndrome indicates a match (0) or conflict (1) in that bit position

Cyclic Codes Can be encoded and decoded using linear feedback shift registers (LFSRs) For cyclic codes, a valid codeword (c0, c1, …, cn-1), shifted right one bit, is also a valid codeword (cn-1, c0, …, cn-2) Takes fixed-length input (k) and produces fixed-length check code (n-k) In contrast, CRC error-detecting code accepts arbitrary length input for fixed-length check code

BCH Codes For positive pair of integers m and t, a (n, k) BCH code has parameters: Block length: n = 2m – 1 Number of check bits: n – k £ mt Minimum distance:dmin ³ 2t + 1 Correct combinations of t or fewer errors Flexibility in choice of parameters Block length, code rate

Reed-Solomon Codes Subclass of nonbinary BCH codes Data processed in chunks of m bits, called symbols An (n, k) RS code has parameters: Symbol length: m bits per symbol Block length: n = 2m – 1 symbols = m(2m – 1) bits Data length: k symbols Size of check code: n – k = 2t symbols = m(2t) bits Minimum distance: dmin = 2t + 1 symbols

Block Interleaving Data written to and read from memory in different orders Data bits and corresponding check bits are interspersed with bits from other blocks At receiver, data are deinterleaved to recover original order A burst error that may occur is spread out over a number of blocks, making error correction possible

Block Interleaving

Flow Control Reasons for breaking up a block of data before transmitting: Limited buffer size of receiver Retransmission of PDU due to error requires smaller amounts of data to be retransmitted On shared medium, larger PDUs occupy medium for extended period, causing delays at other sending stations

Flow Control