ABCN & HCC 29 Feb 2012 Short status Preliminary, not approved ! 2/29/12F. Anghinolfi1

2 ABCN 130 nm Design Tasks ElementWork 1Institute/personStep/issue (Spice or Verilog) Validation Completion Time Estimate CD data formatSpecification Strips readout group Done Readout data formatSpecification Strips readout group Done FE design SpecificationWladek/Jan max strips length ? Chip size OK Q1/Q DesignJan Proto exists, TrimDAC to add Q1/Q FE Bias/DAC & layoutDesignJan + ? Cracow student to work with Jan Q ? Q1/Q BandGapDesignJan FEI-4 bandgap adopted Q1/Q PowerUpDesignJanPending Q1/Q Regulator SpecificationMichalDesign End March 2012 DesignMichal Prototype under evaluation, performance OK Q /29/12

3F. Anghinolfi ABCN 130 nm Design Tasks ElementWork 1Institute/personStep/issue (Spice or Verilog) Validation Completion Time Estimate SLVS I/O DesignPENNAbstract fixed Q ModelsPENN.v model.lib model exist Spice Q Regular I/OStd Cell ?PENN Thick oxide issue : Measurement Undefined RAM blocks RAM protoCERN/ME Delivery Received Functional testsCERN/ME Functional OK Q SEU testFrancis/Bruno Q x128 abstractCERN/ME Obtained Jan x128 abstractCERN/ME Undefined 320x256 abstractCERN/ME Undefined ModelsCERN/ME Under development (updates) No models Critical Command Decoder Verilog codeJoel One running version exists Verilog tested Q TRMJoel ? Q Async/Sync ResetJoel ? Q /29/12

4F. Anghinolfi ABCN 130 nm Design Tasks ElementWork 1Institute/personStep/issue (Spice or Verilog) Validation Completion Time Estimate L1 Data Compression LogicVerilog codeDaniel Verilog tested Change for new MEM Done Watchdog Verilog codeDaniel Not evaluated Done TRM? Q R3 Data Compression LogicVerilog codeSamer Verilog tested Change for new MEM Done Readout Logic Verilog code Joel de Witt Verilog tested Done TRM Joel de Witt ? Q L0/L1 Buffer Verilog codeFrancis Some update envisaged New schema evaluated Done TRMFrancis Not evaluated Done Fast TrackVerilog codePENN RTL Model exists Not evaluated Done Input RegisterVerilog codePENN Evaluated Done Top_Logic Verilog codeGeneva New schema evaluated Change for new MEM Done TRMCERN/Geneva Q /29/12

5F. Anghinolfi ABCN 130 nm Design Tasks ElementWork 1Institute/personStep/issue (Spice or Verilog) Validation Completion Time Estimate FloorplanFirst versionKrzysztof First estimate Drawing only15 Feb 2012 SynthesisFirst VersionKrzysztof Running, for power estimates Running script Q Place & routeFirst VersionKrzysztofQ Functional Tests by simulationVerilog codeFrancis Going on Verilog Q Functional Tests by simulation Verilog code Michelle Going on Verilog Q /29/12

IRRADIATIONS PLANS (update) Front-End Prototype – Xray at low temperature Standby – Low dose rate irradiation Standby – “Beam” hit test vs. special ESD protection (P) Performed by Jan RAM block SEU cross section (P) Under preparation (CERN-ME + FE) SEU standard Logic cross section (with and w/o TRM) Tests on SEULogic performed at IRRAD6 : analysis on going, shows higher sensitivity than expected (early number = 7E-13 cm-2 on a TRM’d logic, but many open questions (beam structure effect …). Another measurements are in preparation in Cracow with a (constant flux) protons beam. 6F. Anghinolfi2/29/12

ABCN Aspect Ratio 7.9 mm Front-End Back-End 6 mm 7.9 mm is target size justified by the 256 channels bonding fanout 6mm is target size justified by the amount of tracks under the chip area (?) Actually fixed according to Ashley’s hybrid design 2/29/12F. Anghinolfi7

ABCN Pins Distribution Data/Xoff Power (Dig, Analog, Vreg Alt Analog Power Front_end (4 rows) BC CLK Com R3 L1 FastTrack Test Pads ID Other 2/29/12F. Anghinolfi8

Power Distribution ABCN 130 power implementation proposal Analog Pads Rails & ESD Digital Pads Rails & ESD gnd! core vddd ext gndd! core vdd! core Analogue core vddd! peri gndd! peri Regulator Digital core vddd! Shunt gndd! Shunt Pad ring power rails cut Regulator vddd! core gnd! SUB vdda ext RegARegD SUB Preliminary, not approved ! 2/29/12F. Anghinolfi9

ABCN 25 Design Issues RAM TIMING MODELS are being updated : may have impact on the L0L1 buffer RTL description Jan’s availability on the Front-End is not 100% 2/29/12F. Anghinolfi10

HCC F. Anghinolfi11 Removed from HCC 2/29/12

HCC F. Anghinolfi12 RTL fixed 2/29/12

HCC F. Anghinolfi13 The tasks marked with ?? may be taken on by M. Key Charriere and Joel De Witt (still not fixed) Geneva University (Designer : Daniel La Marra designer) has agreed to contribute to the HCC Data Concentrator Design RTL code and descriptin fixed Main issue is to resolve the schedule overlap with ABCN (as previously) Priorities will have to be defined (as previously) Both ABCN and HCC Conceptual Design Reviews on MARCH /29/12

ABCN & HCC DESIGN REVIEW 14 AND 15 OF MARCH 2012 at CERN 13:30 to 20:00 BOTH DAYS 14/03 : room 40-R-D10 15/03 : room K01 (ATLAS)(may change) 2/29/12F. Anghinolfi14

ABCN & HCC DESIGN REVIEW Review committee : Alex Grillo - chair Rick Van Berg Ned Spencer Maurice Garcia-Sciveres Ken Wyllie Attendance : Open to anyone (meeting room, EVO and or phone call arrangement) Indico pages under preparation 2/29/12F. Anghinolfi15

ABCN & HCC DESIGN REVIEW Review committee Charge (as listed in previous Conceptual Design Reviews): (1) The specifications are completed and clear. If some points are still a bit fuzzy, the review committee should clarify them or give recommendations in how to clarify them (2) The specifications meet the requirements in terms of: - functionality (architecture, pipeline length, buffers sizes, trigger interface, readout speed,...) - physical dimension (number of channels, bounding pads location,...) - power (maximum allowed dissipated power, power schemes,...) - performance (noise, gain, shaping,...) (3) The design is being done according to the specifications (4) The schedule is reasonable 2/29/12F. Anghinolfi16

ABCN & HCC DESIGN REVIEW 14-Mar-12ABCN 13:30 13:45Introduction to the review and to the ASICS 13:15 14:00Strips readout overview 14:00 14:30ABCN specifications and functions 14:30 15:30Analogue FE 15:30 16:30Analogue blocks (Bandgap, startup, I/Os, power circuits) 30' Break 17:00 20:15 ABCN Digital 17:00 17:15Input Register, Fast Track 17:15 17:30Buffer system 17:30 17:45RAM block 17:45 18:00DCL1 18:00 18:15DCL2 18:15 18:30Readout 18:30 18:45Command Decoder and Registers 18:45 19:10Simulation Test Bench 19:10 19:30Chip simulation status 19:30 20:00Time for reviewers Preliminary planning 2/29/12F. Anghinolfi17

ABCN & HCC DESIGN REVIEW 15-Mar-12HCC 13:30 14:00Issues pending from past day 14:00 14:30ABCN Floorplan, power estimates, roadmap 14:30 15:00HCC specifications and functions 15:00 16:00Analogue blocks (PLL, DLL, I/Os, monitoring …) 30' Break 16:30 17:45 HCC Digital 16:30 16:45Data Concentrator 16:45 17:00Clock and signal generation 17:00 17:15DCS 17:15 17:30Data Encoding 17:30 17:45Command Decoder 17:45 18:15HCC Floorplan, roadmap 18:15 19:00Reviewer session 19:00 19:30End of the Design Review/Early summary Preliminary planning 2/29/12F. Anghinolfi18