State university of New York at New Paltz Electrical and Computer Engineering Department Logic Synthesis Optimization Lect10: Two-level Logic Minimization.

Slides:

Advertisements

Similar presentations

CSEE 4823 Advanced Logic Design Handout: Lecture #2 1/22/15

Advertisements

Based on slides by: Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. ECE/CS 352: Digital System Fundamentals Lecture 8 – Systematic Simplification.

ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions.

Chapter 3 Simplification of Switching Functions

Boolean Functions and their Representations

Give qualifications of instructors: DAP

CS 140 Lecture 4 Combinational Logic: K-Map Professor CK Cheng CSE Dept. UC San Diego 1.

Contemporary Logic Design Two-Level Logic © R.H. Katz Transparency No. 4-1 Chapter #2: Two-Level Combinational Logic Section 2.3, Switches and Tools.

Computer Engineering (Logic Circuits) (Karnaugh Map)

ECE 331 – Digital System Design Karnaugh Maps and Determining a Minimal Cover (Lecture #7) The slides included herein were taken from the materials accompanying.

بهينه سازي با نقشة کارنو Karnaugh Map. 2  Method of graphically representing the truth table that helps visualize adjacencies 2-variable K-map 3-variable.

B-1 Appendix B - Reduction of Digital Logic Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Principles.

1 Simplification of Boolean Functions:  An implementation of a Boolean Function requires the use of logic gates.  A smaller number of gates, with each.

1 Chapter 5 Karnaugh Maps Mei Yang ECG Logic Design 1.

Department of Computer Engineering

CHAPTER 1 INTRODUCTION TO DIGITAL LOGIC. K-Map (1)  Karnaugh Mapping is used to minimize the number of logic gates that are required in a digital circuit.

State university of New York at New Paltz Electrical and Computer Engineering Department Logic Synthesis Optimization Lect19: Multi Level Logic Minimization.

Optimization Algorithm

Two-Level Simplification Approaches Algebraic Simplification: - algorithm/systematic procedure is not always possible - No method for knowing when the.

Examples. Examples (1/11)  Example #1: f(A,B,C,D) =  m(2,3,4,5,7,8,10,13,15) Fill in the 1’s. 1 1 C A B CD AB D 1 1.

Combinational Logic Part 2: Karnaugh maps (quick).

Two Level Networks. Two-Level Networks Slide 2 SOPs A function has, in general many SOPs Functions can be simplified using Boolean algebra Compare the.

Chapter 6 Quine-McCluskey Method Mei Yang ECG Logic Design 1.

Copyright © 2004 by Miguel A. Marin Revised McGILL UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING COURSE ECSE DIGITAL SYSTEMS.

Simplification of incompletely specified functions using QM Tech.

ECE2030 Introduction to Computer Engineering Lecture 8: Quine-McCluskey Method Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering.

CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic 5: Quine-McCluskey Method José Nelson Amaral.

1 ECE2030 Introduction to Computer Engineering Lecture 8: Quine-McCluskey Method Prof. Hsien-Hsin Sean Lee School of ECE Georgia Institute of Technology.

1 Quine-McCluskey Method. 2 Motivation Karnaugh maps are very effective for the minimization of expressions with up to 5 or 6 inputs. However they are.

Chapter 2 Two- Level Combinational Logic. Chapter Overview Logic Functions and Switches Not, AND, OR, NAND, NOR, XOR, XNOR Gate Logic Laws and Theorems.

Computer Engineering (Logic Circuits) (Karnaugh Map)

Chapter3: Gate-Level Minimization Part 1 Origionally By Reham S. Al-Majed Imam Muhammad Bin Saud University.

CS2100 Computer Organisation

07 KM Page 1 ECEn/CS 224 Karnaugh Maps. 07 KM Page 2 ECEn/CS 224 What are Karnaugh Maps? A simpler way to handle most (but not all) jobs of manipulating.

CHAPTER 3: PRINCIPLES OF COMBINATIONAL LOGIC

Ahmad Almulhem, KFUPM 2010 COE 202: Digital Logic Design Combinational Logic Part 3 Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

Boolean Algebra & Logic Circuits Dr. Ahmed El-Bialy Dr. Sahar Fawzy.

CHAPTER 1 INTRODUCTION TO DIGITAL LOGIC

1 Example: Groupings on 3-Variable K-Maps BC F(A,B,C) = A ’ B ’ A BC F(A,B,C) = B ’ A

Key Observation Adjacencies in the K-Map

Digital Logic (Karnaugh Map). Karnaugh Maps Karnaugh maps (K-maps) are graphical representations of boolean functions. One map cell corresponds to a row.

CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic 4: Cost of Logic Circuits and Karnaugh Maps José Nelson Amaral.

Karnaugh Maps (K maps).

EECS 270 Lecture 10. K-map “rules” – Only circle adjacent cells (remember edges are adjacent!) – Only circle groups that are powers of 2 (1, 2,

Lecture 4: Four Input K-Maps CSE 140: Components and Design Techniques for Digital Systems CK Cheng Dept. of Computer Science and Engineering University.

ECE 301 – Digital Electronics Minimizing Boolean Expressions using K-maps, The Minimal Cover, and Incompletely Specified Boolean Functions (Lecture #6)

School of Computer and Communication Engineering, UniMAP DKT 122/3 - DIGITAL SYSTEM I Chapter 4A:Boolean Algebra and Logic Simplification) Mohd ridzuan.

Chapter 3 Simplification of Switching Functions. Simplification Goals Goal -- minimize the cost of realizing a switching function Cost measures and other.

State university of New York at New Paltz Electrical and Computer Engineering Department Logic Synthesis Optimization Lect18: Multi Level Logic Minimization.

©2010 Cengage Learning SLIDES FOR CHAPTER 6 QUINE-McCLUSKEY METHOD Click the mouse to move to the next page. Use the ESC key to exit this chapter. This.

CHAPTER 6 Quine-McCluskey Method

Lecture 6 Quine-McCluskey Method

Lecture 7 Multi-Level Gate Networks

Plotting functions not in canonical form

CS 352 Introduction to Logic Design

Optimized Implementation of Logic Function

Chapter 6 Quine-McCluskey Method

Optimized Implementation of Logic Function

ECE 331 – Digital System Design

Digital Logic & Design Dr. Waseem Ikram Lecture 12.

Digital Logic & Design Dr. Waseem Ikram Lecture 13.

CHAPTER 5 KARNAUGH MAPS 5.1 Minimum Forms of Switching Functions

CH7 Multilevel Gate Network

Optimization Algorithm

Chapter 3 Gate-level Minimization.

Optimized Implementation of Logic Function

COE 202: Digital Logic Design Combinational Logic Part 3

Overview Part 2 – Circuit Optimization

3-Variable K-map AB/C AB/C A’B’ A’B AB AB’

ECE 331 – Digital System Design

Presentation transcript:

State university of New York at New Paltz Electrical and Computer Engineering Department Logic Synthesis Optimization Lect10: Two-level Logic Minimization By Dr. Yaser Khalifa Electrical and Computer Engineering Department State University of New York at New Paltz

Basic Definitions Definition: A Boolean circuit is a directed graph C(G,N) where G are the gates and N  ´G is the set of directed edges (nets) connecting the gates. Some of the vertices are designated: Inputs: I  G Outputs: O  G, I  O =  Each gate g is assigned a Boolean function fg which computes the output of the gate in terms of its inputs.

The fanin FI(g) of a gate g are all predecessor vertices of g: FI(g) = {g’ | (g’,g)  N} The fanout FO(g) of a gate g are all successor vertices of g: FO(g) = {g’ | (g,g’)  N} The cone CONE(g) of a gate g is the transitive fanin of g and g itself. The support SUPPORT(g) of a gate g are all inputs in its cone: SUPPORT(g) = CONE(g)  I

FI(6) = {2,4} FO(6) = {7,9} CONE(6) = {1,2,4,6} SUPPORT(6) = {1,2}

Definitions Implicant: single element of the ON-set or any group of elements that can be combined together in a K-map Prime implicant: implicant that cannot be combined with another implicant to eleminate a term Essential prime implicant: if an element of the ON-set is covered by a single prime implicant, it is an essential prime.

6 Prime Implicants: A’D, CD, AC, BC’D’, A’BC’, ABD’

Essential Prime Implicants: A’D, AC

Minimum Cover = A’D, AC, BC’D’

5 Prime Implicants: A’BC’, A’CD, AC’D, ABC, BD

Essential Prime Implicants: A’BC’, A’CD, AC’D, ABC Minimum Cover = A’BC’, A’CD, AC’D, ABC

Quine-McCluskey Method The QM procedure reduces the minterm expansion of a function to obtain the minimum sum of product. The procedure consists of two main steps described in the following slide.

1.Eliminate as many litrals as possible from each term by systematically applying the theorem XY + XY’ = X. 2.Use a prime implicant chart to select a minimum set of prime implicants which when ORed together, are equal to the function being simplified and which contain a minimum number of literals.

f (a, b, c, d) =  m(0,1,2,5,6,7,8,9,10,14) Is represented by the following minterms Group Group Group Group

What are the Prime Implicants?

Answer: BD’, AB, BC’, AD, B’CD What are the Essential Prime Implicants? Answer: BD’, BC’, AD, B’CD

Cyclic Implicant Chart Cyclic Implicant Chart is a chart which has two or more marks in every row/column. Example: f (a, b, c) =  m(0, 1, 2, 5, 6, 7)

Simplification of Incompletely Specified Functions In the process of finding prime implicants, treat the don’t cares terms as if they were required minterms. Do not worry if this results in an extra prime implicant When forming prime implicant chart do not include don’t care terms.