TOPIC : Types of Simulation UNIT 1 : Modeling Module 1.5 Simulation.

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Presentation transcript:

TOPIC : Types of Simulation UNIT 1 : Modeling Module 1.5 Simulation

Types of Simulation A simulator that executes a compiled code model(e.g. RTL) is referred to as a compiler-code simulator. A simulator that interprets a model based on data structure is said to be table- driven. Activity directed simulation is referred to as event-driven Simulation.

Compiled Simulation Compiled simulation allows the inputs to changed only when the circuit is stable. Input vectors or stimuli are applied at a fixed rate. It is mainly oriented toward functional verification and is not concerned with the timing of the circuit. It evaluates all the elements in the circuit for every input vector.

Example of Compiled Simulation The compiled-code of this circuit is : LDA B AND Q INV STA E OR A STA F STA Q It will simulate for every value of A and B.

Asynchronous circuit with compiled-code model

Event driven Simulation It can process real time inputs, that is, inputs whose times of change are independent of the activity in the simulated circuits. It allows accurate simulation of non- synchronized events such as interrupts or competing requests for use of bus.

Main flow of event driven Simulation

Event-driven Simulation Event: change in logic value at a node, at a certain instant of time  (V,T) Event-driven: only considers active nodes ◦ Efficient Performs both timing and functional verification ◦ All nodes are visible ◦ Glitches are detected Most heavily used and well-suited for all types of designs

Event-driven Simulation Event: change in logic value, at a certain instant of time  (V,T) D=2 a b c Events: Input: b(1)=1 Output: none D=2 a b c Events: Input: b(1)=1 Output: c(3)=0 3

Level of Simulation Register level Simulation : RTL Functional-level Simulation : primitive functional block Gate level Simulation Transistor level Simulation Mixed-level Simulation

Classification of Simulators HDL-based HDL-based: Design and testbench described using HDL ◦ Event-driven ◦ Cycle-based Schematic-based Schematic-based: Design is entered graphically using a schematic editor Emulators Emulators: Design is mapped into FPGA hardware for prototype simulation. Used to perform hardware/software co-simulation.

Classification of Simulators Logic Simulators Emulator-basedSchematic-basedHDL-based Event-drivenCycle-basedGateSystem

Simulation engine Logic simulation of complex VLSI circuits and systems is a time-consuming process. Hardware especially designed to speed-up simulation is called Simulation engines. Simulation engines achieve the speed-up based on two different strategies : model partitioning and algorithm partitioning.

Types of Simulation Engine Model partitioning consists of dividing the model of the simulated circuit into disjoint sub circuits, concurrently simulated by identical processing units (Pus), interconnected by a communication medium. Algorithm partitioning consists of dividing the simulation algorithm into tasks distributed among different Pus working concurrently as stages of a pipeline.