Nanowire Doping via Monolayer Doping Patrick Bennett, AS&T Ho, et. al. Nature Materials 7, 62-67 (2008)

Slides:

Advertisements

Similar presentations

ECE/ChE 4752: Microelectronics Processing Laboratory

Advertisements

CHAPTER 8: THERMAL PROCESS (continued). Diffusion Process The process of materials move from high concentration regions to low concentration regions,

Formation of pn junction in deep silicon pores September 2002 By Xavier Badel, Jan Linnros, Martin Janson, John Österman Department of Microelectronics.

Wally Dream Job.

VLSI Design Lecture 2: Basic Fabrication Steps and Layout

Lecture 11: MOS Transistor

Introduction to CMOS VLSI Design Lecture 0: Introduction

Microelectronics Processing

MSE-630 Dopant Diffusion Topics: Doping methods Resistivity and Resistivity/square Dopant Diffusion Calculations -Gaussian solutions -Error function solutions.

Section 4: Diffusion part 2

X-ray Photoelectron Spectroscopy —— Application in Phase-switching Device Study Xinyuan Wang A

The Deposition Process

ECE/ChE 4752: Microelectronics Processing Laboratory

MEMs Fabrication Alek Mintz 22 April 2015 Abstract

Device Fabrication Example

ECE/ChE 4752: Microelectronics Processing Laboratory

Introduction Integrated circuits: many transistors on one chip.

Wide Bandgap Semiconductor Detectors for Harsh Radiation Environments

Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.

EE415 VLSI Design The Devices: Diode [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.

Fabrication of Active Matrix (STEM) Detectors

PREPARATION OF ZnO NANOWIRES BY ELECTROCHEMICAL DEPOSITION

MOHD YASIR M.Tech. I Semester Electronics Engg. Deptt. ZHCET, AMU.

Gas-to Solid Processing surface Heat Treating Carburizing is a surface heat treating process in which the carbon content of the surface of.

IC Process Integration

SEMINAR ON IC FABRICATION MD.ASLAM ADM NO:05-125,ETC/2008.

MPI Stuttgart Max-Planck-Institut fuer Festkoerperforschung Stuttgart, Germany R. Sordan, K. Balasubramanian, M. Burghard WP2(A): Single fullerene transistor.

SILICON DETECTORS PART I Characteristics on semiconductors.

Elemental silicon is melted and grown into a single crystal ingot Single crystal ingot being grown Completed silicon ingot.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #3. Diffusion  Introduction  Diffusion Process  Diffusion Mechanisms  Why Diffusion?  Diffusion Technology.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #4. Ion Implantation  Introduction  Ion Implantation Process  Advantages Compared to Diffusion  Disadvantages.

Top Down Manufacturing

Application of Silicon-Germanium in the Fabrication of Ultra-shallow Extension Junctions of Sub-100 nm PMOSFETs P. Ranade, H. Takeuchi, W.-H. Lee, V. Subramanian,

Thermal doping review example This presentation is partially animated. Only use the control panel at the bottom of screen to review what you have seen.

Introduction EE1411 Manufacturing Process. EE1412 What is a Semiconductor? Low resistivity => “conductor” High resistivity => “insulator” Intermediate.

Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.

ISAT 436 Micro-/Nanofabrication and Applications Photolithography David J. Lawrence Spring 2004.

CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.

Conductive epitaxial ZnO layers by ALD Conductive epitaxial ZnO layers by ALD Zs. Baji, Z. Lábadi, Zs. E. Horváth, I. Bársony Research Centre for Natural.

Junction Formation The position of the junction for a limited source diffused impurity in a constant background is given by The position of the junction.

Midterm Exam Question (Thermal doping review) This presentation is partially animated. Only use the control panel at the bottom of screen to review what.

High Resolution Depth Profiling of Ti Oxidation

Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1μm MOSFET’s with Epitaxial and δ-Doped Channels A. Asenov and S. Saini, IEEE.

REFERENCE [1] : Jin-Woo Han, Beomseok Kim, Nobuhiko P. Kobayashi, Jing Li, and M. Meyyappan, a simple method for the determination of doping type in nanomaterials.

Neutron Transmutation Doping Conceptual Design Dr. Mosa Othman Silicon doping facility manger Egyptian Second Research Raector (ETRR-2) Atomic Energy Authority.

CMOS FABRICATION.

Research Paper. Chapter 7: DOPANT DIFFUSION DOPANT DIFFUSION Introduction Introduction Basic Concepts Basic Concepts –Dopant solid solubility –Macroscopic.

Graphene Hysteresis Response

Chieh Chang EE 235 – Presentation IMarch 20, 2007 Nanoimprint Lithography for Hybrid Plastic Electronics Michael C. McAlpine, Robin S. Friedman, and Charles.

Boron and Phosphorus Implantation Induced Electrically Active Defects in p-type Silicon Jayantha Senawiratne 1,a, Jeffery S. Cites 1, James G. Couillard.

Diffusion1 Dopant Diffusion (Jaeger Chapter 4 and Campbell Chapter 3) As indicated previously the main front-end processing in building a device or integrated.

Deposition Techniques

Doping. 고려대학교 Center for MNB Sensor Technology 166.

Solid State Devices EE 3311 SMU

Basic Planar Processes

CMOS Fabrication CMOS transistors are fabricated on silicon wafer

MODUL 11 Investigation of Annealing Effect on the Forward bias and Leakage current Changes of P-Type 6H-SiC Schottky Diodes with SiO2 Ramp Profile after.

Date of download: 10/26/2017 Copyright © ASME. All rights reserved.

Bonding interface characterization devices

HG-Cal Simulation using Silvaco TCAD tool at Delhi University Chakresh Jain, Geetika Jain, Ranjeet Dalal, Ashutosh Bhardwaj, Kirti Ranjan CMS simulation.

Example Design a B diffusion for a CMOS tub such that s=900/sq, xj=3m, and CB=11015/cc First, we calculate the average conductivity We cannot calculate.

1.6 Magnetron Sputtering Perpendicular Electric Magnetic Fields.

Chapter 7: DOPANT DIFFUSION

Determining Composition through X-Ray Photoelectron Spectroscopy

EXAMPLE 7.1 BJECTIVE Determine the total bias current on an IC due to subthreshold current. Assume there are 107 n-channel transistors on a single chip,

Multiscale Modeling and Simulation of Nanoengineering:

Basic Planar Process 1. Silicon wafer (substrate) preparation

Presentation transcript:

Nanowire Doping via Monolayer Doping Patrick Bennett, AS&T Ho, et. al. Nature Materials 7, (2008)

Motivation Ions have sufficient energy to pass through a nanowire without stopping, yet still causing serious lattice damage. Spin on techniques lack control and uniformity at the nanoscale. Ho, et. al. Nature Materials 7, (2008)

Process Outline Process carried out in glove box in N 2 environment Ho, et. al. Nature Materials 7, (2008)

Results Low amount of post deposition oxidation (inset unreacted substrate) Dopant profile similar to conventional techniques (limited source) Observed self limiting surface reaction for both P (Diethyl 1-propylphosphonate) and B (allyboronic acid pinacol ester) dopants X-Ray Photoelectron Spectrometry (24 Hrs elapsed) Si-C bond Si-O bond Ambient exposure Ho, et. al. Nature Materials 7, (2008)

Results, continued 33% efficiency of Boron doping (deduced from theoretical coverage and sheet resistance). Cut in half without capping. 95% efficiency for Phosphorus. Due to decreased diffusivity of P in SiO 2 R S std. dev. across sample: 2-5% High reproducibility P B Ho, et. al. Nature Materials 7, (2008)

Dose Modulation Reduction of Binding sites for precursor Mixed solution of blank (dodecene) and dopant (B) precursors Equivalent five and twentyfold decrease in dose suggests similar surface reactivity Tunability of doping via precursor structure Footprint of precursor molecule governs surface concentration 6x reduction in dose using trioctylphosphine oxide (TOP) over DPP 6x footprint Ho, et. al. Nature Materials 7, (2008)

Nanowires Proof of concept: 2 terminal device (back gated) Ohmic contacts formed with DPP n-type switching obtained with TOP(400x enlargement??) I ON /I OFF ratio of D doping profile not modeled. Applied with more success to ultrathin SOI substrates (data not shown) Ho, et. al. Nature Materials 7, (2008)

Summary Novel doping technique Highly controllable in bulk Proof of concept, successfully doped nanowires Ho, et. al. Nature Materials 7, (2008) Comments Carried out in restrictive environment, but not in vacuum (except for capping in e-beam evaporator) Very shallow junction depth Poor control over nanowire doping (expect more papers soon I’d assume)