An ASIC for TOF and DOI Measurement with SiPM Matrices Cristoforo Marzocca, Francesco Licciulli DEI - Politecnico di Bari and INFN - Sezione di Bari, Italy on behalf of INFN 4DMPET collaboration FEE 2014, May 2014, Argonne National Laboratory

 Introduction: the 4DMPET project at INFN  Main requirements for the FE ASIC in 4DMPET  Architecture and building blocks of the analog channel  Structure and features of the 4-channel prototype  Preliminary characterization results  Present and future work Outline 2 FEE 2014, May 2014, Argonne National Laboratory

The INFN 4DMPET project: an overview SiPM array  -photon interaction point visible photons light cone  The detector: continuous fast scintillating crystal coupled on both sides to arrays of Silicon PhotoMultipliers (SiPM)  4D: X and Y of the interaction point; DOI to improve the z resolution; accurate time of the interaction for TOF measurements  Insensitivity to magnetic field for hybrid PET-MRi applications Goals of the project  Timing resolution as low as 200 ps FWHM  X-Y spatial resolution: 1 mm FWHM (charge centroid evaluation)  DOI resolution: 2 mm FWHM  High integration level, compactness, modularity Participants INFN units of Bari, Perugia, Pisa, Torino 3 FEE 2014, May 2014, Argonne National Laboratory

4DMPET: layout of the detection module AB side view C A 48 x 48 x 10 mm3 LYSO scintillator slab:  minimize dead area between blocks B Top and bottom SIPM arrays:  16 x 16 square pixels, 3 mm pixel pitch, 50  m  -cell size C Independent and identical readout boards:  Front-end ASIC  Cluster processor ASIC (FPGA)  Laser driver, photodiode receiver, CK reconstruction ASIC For MRi compatibility  All electric communications through LVDS links  Wire-bonded ASICs (no packages)  Optical links for the external signals 4 FEE 2014, May 2014, Argonne National Laboratory

4DMPET: DOI, timing and energy evaluation  DOI can be estimated with the asymmetry of the Cluster Size in the two tiles z est = estimated z coordinate; D = detector depth; n up = top face cluster size; n down = bottom face cluster size.  Cluster finding algorithms implemented on an FPGA–based cluster processor, for DOI and charge centroid estimation  Energy resolution: 25% FWHM  Low threshold (single phe) for accurate measurements of the interaction time: high resolution Time-to-Digital Converter needed for time measurements (T LSB =100ps)  Exploitation of the TDC for energy measurements: Time over Threshold (ToT) technique 5 FEE 2014, May 2014, Argonne National Laboratory

 Time resolution requirements: minimization of the noise-to-slope ratio  good signal to noise ratio (  20dB for the single micro-cell event)  large bandwidth, (  1GHz) Front-end ASIC: main requirements  Effective solution needed to discriminate the triggers coming from dark pulses generated by the SiPM (especially the multiple ones) SiPM coupled to LYSO crystal: Example of current waveform for 12 phe 6 FEE 2014, May 2014, Argonne National Laboratory

Time over Threshold technique: drawbacks  Simple ToT does not allow to fulfill the energy accuracy requirements for X,Y and DOI evaluation  Simple and effective solution needed to exploit the TDC for the evaluation of energy, so as to avoid the integration of an ADC  Small number of phe:  Inaccuracy in the evaluation of the energy  Large number of phe:  Non-linear behavior Typical scintillation signals Energy evaluation with ToT (distribution) 7 FEE 2014, May 2014, Argonne National Laboratory

Proposed solutions: dark pulse suppression  Dark pulse suppression  Integration of the SiPM current pulse in a short time window TWA, starting from the trigger, (low threshold passed, output signal high) under threshold  invalid signal: integration stopped, channel reset and output signal low over threshold  valid signal, integration goes on in a long time window TWB  Invalid signals are easily identified by theTDC and the circuit is ready to process another input pulse soon after the expiration of the short time window Integrated charge Invalid signal Valid signal TWA low threshold charge threshold trigger low threshold charge threshold trigger 8 FEE 2014, May 2014, Argonne National Laboratory

 Time over Threshold linearization for valid signals  Valid signals are integrated during TWB. At the expiration of TWB, the integration capacitance C INT is discharged at constant current I dis, down to the threshold  The discharge time T dis is proportional to the charge integrated during TWB  The circuit is reset at the end of the discharge and the output signal goes low: its duration ToT is linearly related to the integrated charge, thus to the energy Proposed solutions: energy evaluation with the TDC Integration and constant current discharge Energy evaluation (distributions) TWB T dis T dis =Q INT /I dis ToT=TWB+T dis 9 FEE 2014, May 2014, Argonne National Laboratory

Operation of the FE: simulation at system level Slow comp. out. Output signal Input signal Integrator out. Discharge after TWB Reset after TWA Final reset Simulation of a valid event (10 photons) followed by two dark pulses (TWA=30ns; TWB=100ns; SiPM gain  10 6 ; discharge current 20  A) TWA TWB ToT 10

Z Amplifier Gain Stage LVDS Driver Control Unit Dark Pulse Rejection Y Amplifier Fast Comp ToT Bias Adj Thr SiPM Start Int Reset Adj Ext ResetSPI (config) Start Int Reset Adj Start Int Reset Adj Out Slow Path Fast Path Structure of the analog channel “Fast” path (generation of the trigger):  Transimpedance amplifier  Fast voltage amplifier (gain stage)  Fast comparator “Slow” path:  Font-end transconductance amplifier with two output currents, replicas of the SiPM pulse  Dark pulse rejection module: integration during TWA for signal validation)  Energy evaluation (ToT module): integration during TWB and constant current discharge Control Unit: configuration management, time window, reset and output signal generation 11 I out1 I out2

Fast path preamplifier 12  SiGe 0.35  m (Vdd=3.3V)  HBT’s f T =65GHz  Open loop preamplifier  Ibias adjustable (8 bit DAC)  Timing jitter at the output of the fast comparator  15ps FEE 2014, May 2014, Argonne National Laboratory

Dark pulse rejection block 13  Based on the gated BLR circuit by J.M. Rochelle, D.M. Binkley and M.J. Paulus  The switch and the feedback loop are normally closed to compensate the DC component of the input current, Idc_comp  When the fast path fires, the output pulse ToT goes high, the switch is opened and integration takes place  The output of the comparator is sampled at the expiration of the TWA and is used to accept or reject the event FEE 2014, May 2014, Argonne National Laboratory

 Based on the same gated BLR circuit  The signal dischrg goes high at the expiration of TWB  The comparator fires when the voltage across the integration capacitance is slightly above the baseline Vbl (  V=100mV): the final reset is generated and the output pulse ToT goes low Energy evaluation (ToT) block 14 Vbl+  V FEE 2014, May 2014, Argonne National Laboratory

Some simulations at circuit level 15 Circuit response for different valid input signals (TWB = 230 ns, Idis =1.5  A) Rejection of a 3.3MHz dark pulse train (TWA = 50ns) Circuit response for 10 and 11 photons input signals (time difference 25ns) FEE 2014, May 2014, Argonne National Laboratory

Main features of the channel 16 Configuration  Possible SiPM bias fine adjustment: [800mV ÷ 2.2V], step=13mV  Low threshold adjustment: 8 bits, LSB decided by an external reference current  Time Window A adjustment:[15ns ÷ 150ns], step=0.8ns  Time Window B adjustment:[40ns ÷ 240ns], step=3ns  Threshold for signal validation (charge): [0pC ÷ 6.3pC], step=39fC  Discharge current selection:[1.5μA ÷ 6µA], step=1.5μA Main specs Power supply3.3V Current consumption20 mA Input charge dynamic range30 pC Fast path bandwidth1 GHz Max time-walk200 ps Configuration bits43 Size1.7x0.6 mm 2 Layout of the channel FEE 2014, May 2014, Argonne National Laboratory

The prototype ASIC 17 Digital pads (configuration) Test channel Layout of the ASIC Test channel pads  4 channels + 1 test channel (buffered internal nodes observable)  Technology: SiGe 0.35  m  Size: 5.2 x 2.3 mm 2  Standard SPI interface for the configuration (channels in daisy-chain)  A few prototypes packaged in a CQFP64 ceramic package  All needed voltage and current references internally generated (except the reference current for the adjustment of the low threshold) FEE 2014, May 2014, Argonne National Laboratory

Test of the prototypes 18  Preliminary home-made, two layer board  Charge injected with an injection capacitance: current waveforms similar to the SiPM dark pulses  FPGA development board interfaced with a host PC used for configuration  Automated setting of the low threshold  Output signal ToT converted from LVDS to CMOS standard Waveforms taken on the test channel: buffering of the internal signal not much effective Example of rejected signalExample of valid signal Integrator of the dark pulse suppression block Output pulse Threshold for signal validation Integrator of the energy evaluation block

Some results 19 Test channel voltage references Nominal ValueMeasured Value Band Gap: 1.2 V1.198 V Vref1: 738 mV732 mV Vref2: 2.1 V2.057 V Vref3: 2.2 V2.181 V Fine adjustment of the SiPM bias vs DAC configuration TWA duration vs configuration word: average TWA duration vs configuration word: sigma FEE 2014, May 2014, Argonne National Laboratory

Charge measurements (injection circuit) 20  I dis set at 3  A, TWB varied from 40ns to 240ns by steps of 20ns Input charge Qinj [fC] Output pulse duration ToT [ns] Output pulse duration ToT vs injected charge for different values of TWB FEE 2014, May 2014, Argonne National Laboratory

Charge measurements: dynamic range 21 Injection capacitance: 20pF, 47pF, 330pF Charge step:150 fC Injection capacitance: 1nF Charge step: 500 fC Channel configuration: - TWA = 80 ns - TWB = 200 ns - Discharge current = 4.5  A Output pulse duration ToT [ns] Input charge Qinj [pC] Output pulse duration ToT [  s] Input charge Qinj [pC] Output pulse duration ToT vs injected charge FEE 2014, May 2014, Argonne National Laboratory

Measurements with a SiPM coupled to the FE 22  SiPM Hamamatsu S P (3600 micro-cells, 3mmx3mm, bias voltage=73V, overvoltage=2.4V)  Light source: Picosecond Laser Diode Systems PiLas (40ps pulse width FWHM, 408nm), with optical filter to attenuate the light (about 70%)  Results compared to the ones obtained with a reference preamplifier (discrete OPAMP transimpedance amplifier, Rin=50 , overall voltage gain = 39, BW=100MHz)  Configuration used for the preliminary results: TWA = 80ns, TWB = 200ns, I dis = 4.5  A ref. ampl. 4DMPET Laser power [a.u.] Average no. of photons detected vs laser intensity St. deviation of the no. of detected photons vs laser intensity  Preliminary results, to be validated and analyzed ref. ampl. 4DMPET Laser power [a.u.] Nph: average Nph: standard deviation FEE 2014, May 2014, Argonne National Laboratory

Time measurements 23  SiPM assembled directly on the PCB, as close as possible to the FE input  Measurements of accuracy of the delay between the output pulse and the laser trigger, as a function of the average number of detected photons Time resolution as a function of the average number of detected photons Nph average Time resolution [ps] FEE 2014, May 2014, Argonne National Laboratory

 Design of a new test board, to complete the characterization of the prototypes  Measurements with the SiPM coupled to a scintillator  Coupling of the FE with a CMOS 65nm TDC designed by INFN Pisa within 4DMPET  Realization and characterization of a small detection module with 4x4 SiPMs, 4 ASICs and the TDC Present and scheduled activities FEE 2014, May 2014, Argonne National Laboratory