M.Matveev Rice University March 20, 2002 EMU Muon Port Card Project

One board per CSC Sector (8 or 9 chambers), Resides in the middle of the peripheral VME 9U crate. Receives up to 2 muons from each of 8 or 9 Trigger Motherboards every 25 ns Selects 3 best muons out of 18 possible Transmits these 3 muons in ranked order to Sector Processors residing in the counting room over three 100 m optical cables every 25 ns MPC Functions

VME J1 CONNECTOR CUSTOM PERIPHERAL BACKPLANE 9U x 400 MM BOARD FINISAR FTRJ OPTICAL TRANSCEIVERS TLK2501 SERIALIZERS CCB INTERFACE SORTING LOGIC INPUT AND OUTPUT FIFO VME INTERFACE 3 OPTICAL CABLES TO SECTOR PROCESSOR TMB_1 TMB_2 TMB_3 TMB_4 TMB_5 TMB_6 TMB_7 TMB_8 TMB_9 SER OPTO MPC Block Diagram OPTO SN74GTLP18612 GTLP TRANSCEIVERS FPGA CCB UCLA MEZZANINE CARD (XCV600E)

PIPELINE MUON 1 PIPELINE MUON 2 DFF SORTER “3 OUT OF 18” MUON 1 CCB TMB 1 TMB 2 DFF 4 4 FIFO A FIFO A VME MUX VME TMB 9 MUON 2 VME FIFO_B MUON 1 DFF FIFO_B MUON 2 VME DFF FIFO_B MUON 3 VME MUON 3 54 Sorter FPGA CCB INTERFACE WINNER 9

9 input links from Trigger Motherboards, 80 MHz per link (288 inputs total) 3 output links to data serializers, 80 MHz per link (48 outputs total) 1 output status link (winners) 80 MHz to TMBs Input and output FIFO buffers for testing purposes Interfaces to VME and Clock and Control Board (CCB) (~75 inputs and outputs total for both) FPGA should have ~470 input/output pins and ~28 Gbps total bandwidth FPGA Requirements

TMB - to - MPC Frame Format

MPC – to – SP Frame Format

CSC Numbering scheme In the present design the CSC_ID=1 corresponds to TMB1 on the peripheral backplane, CSC_ID=2 corresponds to TMB2 and so on TMBTMB TMBTMB TMBTMB TMBTMB TMBTMB TMBTMB TMBTMB TMBTMB TMBTMB DMBDMB DMBDMB DMBDMB DMBDMB DMBDMB DMBDMB DMBDMB DMBDMB DMBDMB 1 MPCMPC CCBCCB

Targeted to Xilinx XCV600E-7FG680 FPGA (UCLA mezzanine card) 461/512 input/output pins used (89%) 5009/6912 slices used (72%) 42/72 BlockRAMs used (58%) Mhz maximum performance (FPGA Express synthesis) Latency ns (4.0 BX) total FPGA latency including: BX input 80MHz and multiplexing with FIFO BX sorting “3 out of 18” BX data merging BX output multiplexing and BX data latching into TLK2501 serializers 24 ns serialization delay (TLK MHz) Preliminary results of FPGA Design

GTLP Backplane Interface to 9 TMB’s (completely defined) Mezzanine Card pin assignment done A24D16 VME Interface based on glue logic (address latches, data buffers, comparators, DS/DTACK logic, CSR0) CCB Interface is completely defined Optical Data Format to SP has been agreed Preliminary FPGA design is done (XCV600E-7FG680) MPC draft specification is prepared Schematic design ~80% completed 6 free FPGA were obtained (Xilinx donation) Mezzanine cards are ordered through UCLA MPC Board Design Status

Same CCB for peripheral and Track Finder crates 20 sets (main 9U board + Altera-based mezzanine card) have been fabricated so far 15 boards are assembled and tested 2 boards will be used for Track Finder tests (UF & Rice) CCB for Track Finder Crate

TTCrx Clock40Des1 Jitter Mezzanine CardECP CECP B TTCrx ASIC operating voltage+5.0V+3.3V+5.0V Clock40Des1 jitter, ps (no BC, no L1A) Clock40Des1 jitter, ps (BC commands + L1A) New TTCrxOld TTCrx

Optical Test with TTCrx CCBCCB TTCVITTCVI BIT3BIT3 TTCVXTTCVX OPTOOPTO OPTOOPTO TTCrx ERROR 1 m 100 m VME 9UVME 6U COPPER CABLEOPTICAL CABLE OLD AND NEW TTCrx BOARDS WERE TESTED WITH Mhz CLOCK SOURCE FROM TTCvx MODULE Mhz CLOCK WAS MULTIPLIED BY 2 BY AV9170 CHIP NO ERRORS OBSERVED IN PRBS TEST FROM ONE OPTOBOARD TO ANOTHER AT Mhz (BER < c -1 ) 40 Mhz Clock multiplier PC

TTCrx Clock40Des1 Jitter Conclusion Jitter is lower for the newest TTCrx ASIC (Version 3.1, 12/2001) Jitter increases if the broadcast commands and L1A are transmitted from TTCvi/TTCvx Jitter distribution for ASIC Ver.3.1 is close to gaussian. Jitter distribution for old ASIC looks differently Jitter is lower if the new ASIC is powered from +5V Jitter introduced by any of two TTCrx ASICs and other components in the clock distribution circuitry at our testing setup is tolerable for TLK2501 transceivers operating at Mhz