EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Digital Integrated Circuits A Design Perspective Manufacturing Process Jan M. Rabaey Anantha Chandrakasan.

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Presentation transcript:

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Digital Integrated Circuits A Design Perspective Manufacturing Process Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic July 30, 2002

EE141 © Digital Integrated Circuits 2nd Manufacturing 2 CMOS Process

EE141 © Digital Integrated Circuits 2nd Manufacturing 3 A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process

EE141 © Digital Integrated Circuits 2nd Manufacturing 4 Circuit Under Design

EE141 © Digital Integrated Circuits 2nd Manufacturing 5 Its Layout View

EE141 © Digital Integrated Circuits 2nd Manufacturing 6 The Manufacturing Process For a great tour through the IC manufacturing process and its different steps, check

EE141 © Digital Integrated Circuits 2nd Manufacturing 7 oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process

EE141 © Digital Integrated Circuits 2nd Manufacturing 8 Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

EE141 © Digital Integrated Circuits 2nd Manufacturing 9 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers

EE141 © Digital Integrated Circuits 2nd Manufacturing 10 CMOS Process Walk-Through p + p-epi (a) Base material: p+ substrate with p-epi layer p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask p + p-epi SiO 2 3 SiN 4 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)

EE141 © Digital Integrated Circuits 2nd Manufacturing 11 CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride (e) After n-well and V Tp adjust implants n (f) After p-well and V Tn adjust implants p

EE141 © Digital Integrated Circuits 2nd Manufacturing 12 CMOS Process Walk-Through (g) After polysilicon deposition and etch poly(silicon)

EE141 © Digital Integrated Circuits 2nd Manufacturing 13 CMOS Process Walk-Through

EE141 © Digital Integrated Circuits 2nd Manufacturing 14 Advanced Metallization

EE141 © Digital Integrated Circuits 2nd Manufacturing 15 Advanced Metallization