1 COMP541 Datapaths I Montek Singh Mar 8, 2007

2Topics  Over next 2/3 classes: datapaths  Basic register operations Book sections 7-2 to 7-6 and 7-8 Book sections 7-2 to 7-6 and 7-8  Computer datapaths First part of Chapter 10 First part of Chapter 10

3 Parts of CPUs  Datapath The registers and logic to perform operations on them The registers and logic to perform operations on them  Control unit Generates signals to control datapath Generates signals to control datapath

4 Memory and I/O  Are connected to the data/control in and out lines Example: register to memory ops Example: register to memory ops

5Microoperations  Basic operations of the datapath Example: moving data from one register to another Example: moving data from one register to another  Not necessarily microprogrammed control Just a description of operations Just a description of operations  Microoperation expected to complete in one clock  Register transfer notation, next

6 Register Transfer Language (RTL)  Registers named in uppercase PC, IR (instruction), R3 PC, IR (instruction), R3 Little endian Little endian

7RT  Transfer from R1 to R2 R2  R1 R2  R1 R2 is destination R2 is destination R1 is source R1 is source  Conditional If(K1 = 1) then (R2  R1) If(K1 = 1) then (R2  R1) K1: R2  R1 as a shorter form K1: R2  R1 as a shorter form

8Transfer  Transfer at the clock edge  When K1 is high  n bits wide

9Symbols  Note memory transfers

10 Syntax not Verilog (but similar)

11 Types of Microoperations  Transfer – have just looked at  Arithmetic  Logic  Shift

12Arithmetic  Basic ops (not multiply, divide) R0  R1 + R2 R0  R1 + R2  Subtraction by 2’s complement

13 Notation is Shorthand for Hardware  Consider and and  Note overflow and carry registers

14 Logic Microoperations  OR notation a little confusing shows two types of syntax for ORs shows two types of syntax for ORs

15 Shift Microoperations  Here just the basic one-bit shifts  Bit falls off the end, zero shifted in

16 Multiplexer-Based Transfers  Consider  Which can also be expressed as  Block diagram next

17 Multiplexer Block Diagram  Detailed block diagram next

18Detailed  Simpler version is easier to follow and to derive

19 Bus-Based Transfers  How about when there are lots of registers? Beyond a certain point muxes become unwieldy Beyond a certain point muxes become unwieldy  Can use buses and send data over common set of wires

20 Simple Cases  One mux  One output bus

21Transfers  Can’t be as general  Only single source  About ½ the hardware

22 Three-State Bus  Remember three-state drivers allow having multiple outputs share wire  Have to control so only one is asserted  Example next

23 Same Example with 3-State  One R output Enable controls Enable controls  Load controls which latches  Fewer wires  Especially important outside chip

24 Memory Transfers  Usually one or more buses associated with memory Address Address Data Data  Note that memory can be slower, so may have to use complex timing Address on one clock cycle Address on one clock cycle Data latched at later clock cycle Data latched at later clock cycle

25Datapath  Blue signals generated by control  A&B buses to ALU B can be constant from memory B can be constant from memory Can also send addr and data Can also send addr and data

26 R1  R2+R3  Signals Load enable Load enable A, B select A, B select MB Select MB Select MF Select MF Select G Select G Select Destination (D) Destination (D)  What about timing?

27Timing  All can occur in one clock, but  Signals must be available in time to propagate through muxes, ALU and  Be at R inputs by next posedge  Go back and look at path

28Next  Look at specific MIPS design  Next time Continue design review of ALU Continue design review of ALU Look at shifter Look at shifter