Structure and Role of a Processor

The Registers………….

What are Registers? Special storage locations stored in the circuitry of the processor They hold information temporarily while it is being decoded or manipulated We will look at 6 different registers…….

1. The Program Counter (PC) AKA the sequence control register (SCR) or the sequence register It holds the address of the next instruction to be executed When a sequence of instructions are being executed the program counter will be incremented to point at the next instruction

2. General Purpose Registers Some computers have up to 16, some only have one called an accumulator They perform arithmetic functions an example being: Load contents of 1000 into the accumulator Add contents of 1001 into the accumulator Store contents of accumulator into 1002 Note 1000, 1001 and 1002 are memory locations

The Current Instruction Register (CIR or IR) Contains the operator and operand of the current instruction E.g. Load contents of location 1000 into the accumulator LDA 1000

4. The Memory Address Register (MAR) Holds the address of memory locations from which data will be read or written to Instructions are also held in memory so it will also hold the address of instructions to be fetched Addresses for the next instructions are copied to this register from the Program counter when needed

5. The Memory Data Register (MDR) AKA the Memory Buffer Register (MBR) Data being read from or written to memory is temporarily stored here All transfers to memory to the CPU go via this register to act as a buffer to compensate for the difference in speed between memory and the CPU

5. The Status Register (SR) AKA Program Status Words or PSW Holds information about the result of instructions E.g. one bit will be set if an overflow occurs, another if the last instruction was negative The CPU can use this information to decide whether it needs to branch out of sequence It also hold info on interrupts

Task Read the paragraph – inside the CPU on page 200 Draw the diagram shown on page 200 on A4 paper – landscape and label what each register/unit does using the info on pages 200 and 2001

Fetch Decode Execute

Instruction Register CIR Arithmetic Logic Unit General Purpose Registers Current Instruction Register CIR Status Register SR Program Counter PC Control Unit Memory Address Register MAR Memory Data Register MDR

Instruction Register CIR Fetch – Step 1 Arithmetic Logic Unit General Purpose Registers Current Instruction Register CIR Status Register SR Program Counter PC INSTRUCTION 1 ADDRESS Control Unit Memory Address Register MAR Memory Data Register MDR

Instruction Register CIR Fetch – Step 1 Arithmetic Logic Unit General Purpose Registers Current Instruction Register CIR Status Register SR Program Counter PC INSTRUCTION 1 ADDRESS COPY Control Unit INSRUCTION 1 ADDRESS Memory Address Register MAR Memory Data Register MDR

Instruction Register CIR Fetch – Step 2 Arithmetic Logic Unit General Purpose Registers Current Instruction Register CIR Status Register SR Program Counter PC INSTRUCTION 1 ADDRESS INSTRUCTION 1 RETRIEVED FROM MEMORY AND COPIED HERE Control Unit INSRUCTION 1 ADDRESS Memory Data Register MDR Memory Address Register MAR

Instruction Register CIR Fetch – Step 2 Arithmetic Logic Unit General Purpose Registers Current Instruction Register CIR Status Register SR Program Counter PC INSTRUCTION 2 ADDRESS INSTRUCTION INCREMENTED BY 1 INSTRUCTION 1 RETRIEVED FROM MEMORY AND COPIED HERE Control Unit INSRUCTION 1 ADDRESS Memory Data Register MDR Memory Address Register MAR

Instruction Register CIR Fetch – Step 3 Arithmetic Logic Unit INSTRUCTION 1 General Purpose Registers Current Instruction Register CIR Status Register SR Program Counter PC INSTRUCTION 2 ADDRESS COPY INSTRUCTION 1 Control Unit INSRUCTION 1 ADDRESS Memory Data Register MDR Memory Address Register MAR

Instruction Register CIR Decode – Step 1 INSTRUCTION HELD IN CIR IS DECODED Arithmetic Logic Unit INSTRUCTION 1 General Purpose Registers Current Instruction Register CIR Status Register SR Program Counter PC INSTRUCTION 2 ADDRESS INSTRUCTION 1 Control Unit INSRUCTION 1 ADDRESS Memory Data Register MDR Memory Address Register MAR

Instruction Register CIR Execute – Step 1 INSTRUCTION HELD IN CIR IS EXECUTED Arithmetic Logic Unit INSTRUCTION 1 General Purpose Registers Current Instruction Register CIR Status Register SR Program Counter PC INSTRUCTION 2 ADDRESS INSTRUCTION 1 Control Unit INSRUCTION 1 ADDRESS Memory Data Register MDR Memory Address Register MAR

No START Any Instructions to Execute Fetch next Instruction Decode Instruction Execute Instruction` Any Interrupts To Process Transfer control to Interrupt Handling Program

Fetch Execute Cycle in Register Transfer Notation MAR [PC] MDR [Memory Location] PC [PC1] + 1 CIR [MDR]

Task Make your own diagram / notes regarding the Fetch – Execute Cycle that you could revise from (use page 202 to help you) Then attempt Q1 on page 202 to ensure you understand it

Task Do question 1 on page 202 Answer below in white: Instruction address 500 in PC copied to MAR Location 1000 contents copied to MDR Instruction address 503 in program counter Location 1000 contents copied from MDR to CIR

What happens if there is an interrupt? There is a special register called a stack pointer If there is an interrupt, the current contents of all the registers are stored on the stack and the stack pointer is updated Stacks can be used instead of general purpose registers to hold intermediate results of arithmetic operations (a return instruction brings results back)

Interrupts When a device seeks the attention of the processor…………. Any program being executed is suspended and control passes over to an interrupt service routine

Types of Interrupt Input / Output (I/O) Timer Interrupt – certain functions are performed at regular intervals Program Check Interrupt – caused by an error in a program e.g. division by zero Machine Check interrupt – machine malfunction There is an Interrupt Register in the CPU and interrupts are assigned different levels of priority. Some interrupts are dealt with immediately, some are not

Interrupt Priorities HARDWARE FAILURE (Machine Check interrupt) Program Check Interrupt Timer Interrupt – certain functions are performed at regular intervals Input / Output (I/O)

Interrupt service routine, or interrupt handler sequence if there is an interrupt: Complete current fetch execute cycle Next instruction location on program counter is stored on stack Contents of other registers are stacked Interrupt source is identified Other Lower priority interrupts are disabled Program counter is loaded with the address of Interrupt service routine Interrupt service routine is executed Contents of stack are restored to registers Interrupts are re-enabled Program counter is restored to point to next instruction

Vectored interrupt mechanism A complete list of interrupts and associated starting addresses are stored in the Interrupt vector table All interrupts have a base address (in the table) and the exact location of a particular interrupt is found by adding and offset address supplied by the interrupting device The base address plus the offset are copied to the program counter

Note Ask for handout on interrupts!

Processor performance is determined by Clock Speed Word Length Bus Width Read and make notes about these aspects on pages 205 and 206 then do questions and exercises on page 206

Task Read the recap and then do Q3 on page 203