Pre-Processing Filter for Audio Applications By Nathan Shaw, Lerzan Celikkanat, and Xiangfeng Wang ELEC 422 VLSI Design 1 Fall 2005

Overview  Implementing a low pass FIR filter 4 taps 4 taps  8-bit I/O, Two’s Complement  Major Components: FIFO FIFO 8-bit multiplier 8-bit multiplier 16-bit adder 16-bit adder PLA: control unit/ROM PLA: control unit/ROM

Filter Block Diagram

ROM  6 words x 8-bits  Coefficient determined by Control Unit by way of decoder

Control Unit  INPUTS: Restart FailSafe NewInput;  OUTPUTS: S1 S2 S3 C0 C1 C2 Shift LoadI LoadC LoadMul LoadX LoadSum LoadFinal Clr1 Clr2

WAIT Select coeff α3 GOTSIGNAL Load signal S2=0 IDLE Clear registers Load RAM with zeros SHIFT 3 times MUL LoadI=1 LoadC=1 ADD LoadMul=1 LoadX=1 SUM LoadSum=1 STORE LoadX=1 Clr1=1 State Machine Shift Select next coeff X 4 FINAL LoadFinal=1 BYPASS S3=1 LoadI=1 (0,d) (1,d) (d,1)

16-bit Carry Ripple Adder  Composed of four 4-bit carry ripple adders  Two 16-bit inputs and one 16-bit output

Multiplier  8 bit x 8 bit  16 bit output

Multiplier

FIFO  8 elements deep  8 bits wide

Output => α 3 *x 0 + α 2 *x 1 + α 1 *x 2 + α 0 *x 3 + x 4 x4x4x4x4 x3x3x3x3 x2x2x2x2 x1x1x1x1 x0x0x0x0 x0x0x0x0 X4X4X4X4 X3X3X3X3 X2X2X2X2 x1x1x1x1 x4x4x4x4 x3x3x3x3 x2x2x2x2 x1x1x1x1 x0x0x0x0 x1x1x1x1 x0x0x0x0 x4x4x4x4 x3x3x3x3 x2x2x2x2 x4x4x4x4 x3x3x3x3 x2x2x2x2 x1x1x1x1 x0x0x0x0 x3x3x3x3 x2x2x2x2 x1x1x1x1 x0x0x0x0 x4x4x4x4 x4x4x4x4 x3x3x3x3 x2x2x2x2 x1x1x1x1 x0x0x0x0 x2x2x2x2 x1x1x1x1 x0x0x0x0 x4x4x4x4 x3x3x3x3 shift1shift2shift6shift4shift5 * α 3 shift7shift3 * α 2 * α 1 * α 0 * 1

Outputs  T0 => x 0  T1 => α 0 *x 0 + x 1  T2 => α 1 *x 0 + α 0 *x 1 + x 2  T3 => α 2 *x 0 + α 1 *x 1 + α 0 *x 2 + x 3  T3 => α 3 *x 0 + α 2 *x 1 + α 1 *x 2 + α 0 *x 3 + x 4  Tn => α 3 *x n-3 + α 2 *x n-2 + α 1 *x n-1 + x n