Processor Organization and Architecture Module III

Control Unit

Micro-operations Program : Sequence of instructions Instruction Cycle: Fetch, Indirect, Execute & Interrupt To design control unit : further subdivision is required Each of the smaller cycle involves processor registers and they are called micro-operations Micro-operations are atomic operations of a processor

Fetch Cycle

Processor Registers for Fetch Cycle Memory Address Register (MAR) – Connected to address bus – Specifies address for read or write operation Memory Buffer Register (MBR) – Connected to data bus – Holds data to write or last data read Program Counter (PC) – Holds address of next instruction to be fetched Instruction Register (IR) – Holds last instruction fetched

Fetch Sequence Address of next instruction is in PC

Fetch Sequence Step 1: Move address in PC to MAR

Fetch Sequence Step 2: To bring instruction 1.The address is placed on address bus from MAR 2.Control unit issues READ command on control bus 3.Data is kept on data bus which is copied to MBR & PC is incremented by 1

Fetch Sequence Step 3: Move contents of MBR to IR

Fetch Sequence Address of next instruction is in PC Step 1: Move address in PC to MAR Step 2: To bring instruction 1.The address is placed on address bus from MAR 2.Control unit issues READ command on control bus 3.Data is kept on data bus which is copied to MBR & PC is incremented by 1 Step 3: Move contents of MBR to IR

Fetch Cycle It involves 3 steps and 4 micro-operations. Each micro-operation involves movement of data into or out of a register As long as they do not interfere each other, multiple micro-ops can take place in one step.

Symbolic Representation t1:MAR <- (PC) t2:MBR <- (memory) PC <- (PC) +1 t3:IR <- (MBR) or t1:MAR <- (PC) t2:MBR <- (memory) t3:PC <- (PC) +1 IR <- (MBR)

Rules for Grouping of Micro- operations 1. The proper sequence of events must be followed. – (MAR  (PC)) must precede (MBR  Memory) because it should makes use of the address in MAR. 2. Conflicts must be avoided. – One should not attempt to read to and write from the same register in one time unit. – E.g. (MBR  Memory) and (IR  MBR) should not occur during the same time unit.

Functional Requirements for Control Unit 3 step process to implement control unit 1.Define the basic elements of the processor. 2.Describe the micro-operations that the processor performs. 3.Determine the functions of control unit to perform the micro-operations.

Basic elements of the Processor ALU Registers Internal data paths External data paths Control unit

Micro-operations All micro-operations fall into one of the following categories: Transfer data from one register to another. Transfer data from a register to an external interface (e.g., system bus). Transfer data from an external interface to a register. Perform an arithmetic or logic operation, using registers for input and output.

Functions of Control Unit Sequencing: The control unit causes the processor to step through a series of micro- operations in the proper sequence, based on the program being executed. Execution: The control unit causes each micro-operation to be performed.

Control Unit Specifications External : It must have – Inputs : to determine the state of the system and – Outputs : to control the behaviour of the system. Internal: It requires a logic to perform its sequencing and execution functions.

Block Diagram of Control Unit

Inputs to Control Unit Clock – One micro-operation (or set of parallel micro- operations) per clock cycle Instruction Register – Op-code and addressing mode of current instruction to determine which micro-operations need to be performed Flags – Status of CPU and outcome of previous ALU operations Control Signals from control bus – Signals to control unit like Interrupts and Acknowledgements

Outputs from Control Unit Control Signals within CPU – Cause data movement between registers – Activate specific ALU functions Control Signals to control bus – To memory – To I/O modules

Control Signal Example

It has single accumulator(AC). Data paths are shown Termination of Control signals are shown C i and indicated by a circle With each clock cycle, CU reads all its input and emit a set of control signals