doc.: IEEE /0146r1 Submission March 2005 John Benko, Marie-Helene Hamon, France TelecomSlide 1 Advanced Coding Comparison Marie-Helene Hamon, John Benko France Telecom Claude Berrou ENST Bretagne Jacky TouschTurboConcept Brian EdmonstoniCoding

doc.: IEEE /0146r1 Submission March 2005 John Benko, Marie-Helene Hamon, France TelecomSlide 2 Outline Coding proposals in TGn Advanced FEC Code Requirements for TGn Comparing Codes LDPCC vs. Turbo Codes Facts & Recommendations

doc.: IEEE /0146r1 Submission March 2005 John Benko, Marie-Helene Hamon, France TelecomSlide 3 Coding Proposals in TGn (Historical) Partial (13): –NokiaLDPC –Infocomm ResearchLDPC –ST MicroLDPC –NortelLDPC –PanasonicLDPC –HughesLDPC –InprocommLDPC –Sharp7/8 CC –PhilipsConcatenated RS –TrelliswareHybrid LDPC/TurboCode –France TelecomTurbo Code –MotorolaTurbo Code –WwiseTurbo Code Full: –TGnSyncLDPCOptional –Wwise LDPCOptional –MitMotTurbo CodeOptional –QualcommNone

doc.: IEEE /0146r1 Submission March 2005 John Benko, Marie-Helene Hamon, France TelecomSlide 4 Advanced FEC Code Requirements Performance –Much better than a CC –Must have good performance for all blocksizes (small as well as large) Small blocksize example: VoIP packets (as small as 50 bytes) Large blocksize example: Streaming HD-Video Latency –Low, < 6 us –Good performance with a small number of iterations Implementation –Low Cost – small die size (memory and logic) –Mature, – Chipsets require fast time to market Should not be held up due to a FEC without a well-defined implementation

doc.: IEEE /0146r1 Submission March 2005 John Benko, Marie-Helene Hamon, France TelecomSlide 5 Complexity Comparison Chip Area –Number of Gates –Technology used (ex. ASIC 0.13 mm, average density of 222 kgates/mm 2 ) –Degree of Parallelism (relates also to max decoded bit-rate) Latency < 6 ms –Number of Iterations –Degree of Parallelism –Clock Frequency used (typical F clk =200 MHz) CodeMax Encoded Block Size F clk MHz PN it Total Memory Decoded Rate(Max) Max Latency Area (.13 mm) Turbo Code* duo-binary 2048 bits kbits320 Mbps 4.8  s 1.4 mm kbits480 Mbps 3.2  s 2.0 mm kbits200 Mbps 5.12  s 2.0 mm 2 Wwise LDPC bits240?12?300 Mbps 6.0  s ? Sync LDPC 1728 bits??????? *Estimates from [4] +Estimates from [1]

doc.: IEEE /0146r1 Submission March 2005 John Benko, Marie-Helene Hamon, France TelecomSlide 6 ST-Micro (Wwise)* LDPCC vs. TC SISO AWGN BPSK + N=1744 bits Wwise LDPCC -972 bits (121.5 bytes) 12i => 600kGates, 6 us Duo-Binary TC -976 bits (122 bytes) 8i, P=12 => 2.0 mm 2, 5.12 us TGnSync LDPCC -Equivalent not found *Wwise Results from Berlin presentation [1] + BPSK, R=1/2 proposed as optional mode in Wwise

doc.: IEEE /0146r1 Submission March 2005 John Benko, Marie-Helene Hamon, France TelecomSlide 7 Wwise LDPCC*, TC and CC 2x2 SDM, AWGN 64-QAM, R=3/4 Gains over PER TC : ~3.2 dB (8 iterations) LDPCC: ~2.4 dB (12 iterations) *Wwise Results taken from [2] TC LDPCC CC

doc.: IEEE /0146r1 Submission March 2005 John Benko, Marie-Helene Hamon, France TelecomSlide 8 LDPCC from.16e* *LDPCC here [3] is slightly different from what is used in TGnSync SISO, AWGN, QPSK, R=1/2 LDPCC - 50 iterations (unrealistic) TC - 8 iterations (realistic) TC Gains over PER N=2304: 0.2 dB N=576 : 0.3 dB (increase with smaller block size) TC LDPCC

doc.: IEEE /0146r1 Submission March 2005 John Benko, Marie-Helene Hamon, France TelecomSlide 9 LDPCCs vs. Turbo Codes (TCs) LDPCCs History Discovered in 60’s by Gallager -Implemented only in past few years -Original Patent expired, but -Since March 2001, 152 Patents have been applied for/ granted concerning LDPCCs [5] Technology New Development -Hot Research Topic at many universities -No common implementation available Performance* Improves as the block size increases TCs History Discovered in early 90’s by Berrou, et al. -Patents exist, but -Well defined licensing program Technology Mature, Stable -Well established & implemented -Ongoing Research at select universities - Turbo Decoders are already available (Implementation targeted for ASIC, but also FPGA) Performance* Good performance for all.11n block sizes (given latency requirements) *Generalization

doc.: IEEE /0146r1 Submission March 2005 John Benko, Marie-Helene Hamon, France TelecomSlide 10 Facts & Recommendations Modularity –Performance of the FEC code is independant of system –Codes proposed can be easily put in WWise and TGnSync Difficult to compare –From FRCC, code performance seen only in context of full system –Current two proposed specfications differ Wwise nor TGnSych provided simulation results for their code with other proposal –Codes compared in performance should be of similar complexity –Very little complexity results have been seen to this date Mature code –Enables pre and 1 st production devices to ship with advanced coding options. Action Item? –We need to re-think(create) the advanced coding selection process or we might get stuck with an advanced coding scheme that is not in the best interest of the n –Suggestion: Form a separate coding sub-group

doc.: IEEE /0146r1 Submission March 2005 John Benko, Marie-Helene Hamon, France TelecomSlide 11 References [1] IEEE /400r4, " ST Microelectronics LDPCC Partial Proposal for n CFP”, ST Micro, September [2] IEEE / n, “WWiSE proposal response to functional requirements and comparison criteria.” [3] IEEE e-0/006, " LDPC Coding for OFDMA PHY", January [4] IEEE /1382r1, "Turbo Codes: Complexity Estimates", TurboConcept France Telecom R&D, November [5] [6] C. Berrou, A. Glavieux, P. Thitimajshima, "Near Shannon limit error- correcting coding and decoding: Turbo Codes", ICC93, vol. 2, pp , May 93. [7] C. Berrou, "The ten-year-old turbo codes are entering into service", IEEE Communications Magazine, vol. 41, pp , August 03. [8] C. Berrou, M. Jezequel, C. Douillard, S. Kerouedan, "The advantages of non-binary turbo codes", Proc IEEE ITW 2001, pp , Sept. 01.