Peter W Phillips Ashley Greenall Matt Warren Bruce Gallop 08/02/2013

Recall: ABCN25 Functional Test Passive Probe Card Bonded Chip Card & Common Driver “Driver” board is actually just a buffer and MUX, really driven by NI hardware 2

Recall: ABCN25 Wafer Test Digital Test Vectors supplied by Francis Anghinolfi as.vcf files Block A CV Block B CI W shunt Block C CI M shunt1 Block D CI M shunt2 DVM measurements DAC linearity using ABCN internal MUX Vout from internal LDO Analogue Tests Two Point Gain Two Point Trim 3 Wafer A5GJ0HX

ABC130 Test Proposal SAMTEC Standard Probe card ends in 0.1” pitch header: add mezzanine PCB to adapt to hybrid compatible SAMTEC ABC130 “Baby” Sensor (optional) HV Propose companion single chip PCB with identical SAMTEC pinout. This takes one ABC130 and (optionally) a “baby” strip sensor SAMTEC Driver PCB HSIO DVM 4

100  Not to scale! 100nF Edge Sensor wired to A9, A10 ? ABC nF NB graphic is not an exact match with “ABC_Pads_V5.2.pdf” – revision needed Analogue MUX pads here??? PROVISIONAL 5

Functional Test Digital Test Vectors – Block A CV – Block B CI Will the design team provide these? DVM measurements – DAC linearity using ABC130 internal MUX – Vout from internal LDO Analogue Tests – Two Point Gain – Two Point Trim Driver needs extra circuitry over that needed for hybrids – Address & Enable lines Perhaps place analogue extras on mezzanine / single chip card – Analogue switch and shunt control block – Routing of MUX output to DVM 6

7 Planning for ABC130 Hybrids – without HCC ABC130 and HCC submissions being done sequentially Results in ABC130 arriving ~3(?) months before HCC Should plan for ABC130 evaluation without HCC First at single chip level – followed by hybrid and then module Important to confirm that ABC130 works as expected when attached to a sensor Propose using an FPGA in place of HCC Acts as a ‘blank canvas’ – program to suit required configuration Aim for modular system providing seamless migration from wafer probing up to module level Speeds up evaluation of ASIC(s) at all levels of testing as DAQ changes are minimised Will impact upon hybrid layout – not realistic to add FPGA to a hybrid First hybrids will be exclusive of HCC All ABC130 – HCC connectivity will now be brought to edge of hybrid Will firstly hook up to FPGA which is mounted external to hybrid to access digital I/O Followed by HCC on plug-in For Plug-in candidate FPGA device identified – Xilinx Spartan 3AN series (XC3S50AN) Single chip solution offering integrated configuration memory, 2 x DCMs, 50 diff I/O, LVCMOS

8 Testing ABC130s at different stages – without HCC HSIO DAQ FPGA Wafer Probing Driver Board Module Test Driver Board designed to connect directly to Wafer probe card Hybrid test panel (hybrids tested individually) Module test frame without FPGA plug-ins FPGA plug-ins come later (if required) If using Driver board would require 2 off for a module Hybrids on Panel Provides both digital and analogue functionality – required for wafer probing

9 Testing modules – without HCC Hybrid To DAQ (only required if plug-ins used) Samtec SFMH series 50 pin connector (1.27mm pitch) 40 x 60mm Samtec FTSH series 50 pin connector Symmetric Module Future proof - replace Spartan with HCC HCC Drawn to scale to show that 2 plug-ins can fit adjacent to a module Driver board(s) connect directly to frame (bypass plug-ins)

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HSIO FPGA Main Logic Ethernet Clocks ABC Emu Verilog code from ABC130 SVN Verilog code from ABC130 SVN Compiled for FPGA (Xilinx Virtex-4) on HSIO Compiled for FPGA (Xilinx Virtex-4) on HSIO Needed to bypass tri-state outputsNeeded to bypass tri-state outputs Replaced large RAMs with FPGA-BlockRAM blockReplaced large RAMs with FPGA-BlockRAM block Removed “ChannelNN” registers – logic too big for FPGA timingRemoved “ChannelNN” registers – logic too big for FPGA timing Wrapped in VHDLWrapped in VHDL Added to the HSIO readout firmware Added to the HSIO readout firmware Top level block connected as if external (except for IDELAY)Top level block connected as if external (except for IDELAY) Additional firmware to handle new data format, rate and framingAdditional firmware to handle new data format, rate and framing 80 or 160Mb rates, ABC or HCC formats handled80 or 160Mb rates, ABC or HCC formats handled ABC130 in HSIO FPGA PC SCTDAQ 11

ABC130 in SCTDAQ ABC130 appears as a special input streamABC130 appears as a special input stream HSIO decodes packets to a 64-bit aligned sequenceHSIO decodes packets to a 64-bit aligned sequence Send bit data to ABC on one of 4 streamsSend bit data to ABC on one of 4 streams Recent addition is the option of a timed L0Recent addition is the option of a timed L0 For “CAL+L1A”, but tested with BCR + L0For “CAL+L1A”, but tested with BCR + L0 SCTDAQ sends commandsSCTDAQ sends commands Mapping old to newMapping old to new BCR -> BCRBCR -> BCR Soft Reset -> L0IDReset (Aim is to know next L0)Soft Reset -> L0IDReset (Aim is to know next L0) L1 -> L0 + L1 + (R3)L1 -> L0 + L1 + (R3) keeps track of L0 since resetkeeps track of L0 since reset each is a separate command to HSIO so asynchronouseach is a separate command to HSIO so asynchronous 12

N-Mask test Using test mode (put mask into pipeline)Using test mode (put mask into pipeline) Here collected in 1BC mode, can also use 3BCHere collected in 1BC mode, can also use 3BC Mask is set by bitMask is set by bit Readout interleavedReadout interleaved Also see R3Also see R3 (ignored for time-being) 13

Now and Next Latest NewsLatest News Emulation now includes 2 ABCN chips (today).Emulation now includes 2 ABCN chips (today). XON / XOFF and data output seem OKXON / XOFF and data output seem OK as 2 separate chips (128 ch each)as 2 separate chips (128 ch each) Find more similarities to ABCNFind more similarities to ABCN Next StepsNext Steps PCB kick-off meeting on 21 st FebruaryPCB kick-off meeting on 21 st February 14