ENGG 340 Midterm Review

Introduced the Concept of Variables and Functions Introduced the Concept of AND, OR, and NOT Introduced the Concept of Truth Tables Introduced the Concept of Logic Gates Introduced the Concept of Logic Networks Introduced the Concept of Logic Network Analysis –Truth Table, Equation, and Timing Diagram (functional & timing) Introduced the Concept of Logic Network Synthesis Introduced the Concept of Functionally Equivalent Circuits

Boolean Logic Should Absolutely Know/Understand/Utilize 1a = 0 1b = 1 2a = 1 2b = 0 3a = 1. 0 = 0 3b = = 1 4a. If x = 0 then !x = 1 4b. If x = 1 then !x = 0

5a. x. 0 = 0 5b. x + 1 = 1 6a. x. 1 = x 6b. x + 0 = x 7a. x. x = x 7b. x + x = x 8a. x. !x = 0 8b. x + !x = 1 9 !!x = x Also should Absolutely Know/Understand/Utilize DeMorgan’s Theorem 15a. !(X. Y) = !X + !Y 15b. !(X + Y) = !X. !Y

Introduced Concepts of Algebraic Manipulation Venn Diagrams

Synthesis/Design Steps Assign variable names and functions Create truth table Write Sum of Products or Product of Sums Create Schematic or HDL

Terminology You Should Know Cost SoP form PoS form Minterm/Maxterm NAND and NOR Gates via DeMorgan’s Theorem Bubble Logic = =

Optimization Techniques Algebraic Manipulation Karnaugh Maps –Literals –Implicants –Prime Implicants –Cover That there are other Optimization techniques

Logic Gate Basics Transistors Operated in Cut-off and Saturation CMOS – Complementary MOS –PUN/PDN

Logic Gate Static and Dynamic Characteristics Voh/Vol Vih/Vil Noise Margin Propagation Delay Rise and Fall Times Fan In and Fan Out

Types of Integrated Circuits

Know commonly used combinational subcircuits –Multiplexers –Decoders –Encoders

VHDL ENTITY –Inputs and Outputs ARCHITECTURE –Functional Description VECTORS AND, OR, NOT

SELECT – not in a PROCESS WITH s SELECT f <= w0 WHEN '0', w1 WHEN OTHERS ; CONDITIONAL – not in a PROCESS f <= w0 WHEN s = '0' ELSE w1 ; CASE – in a PROCESS CASE s IS WHEN '0' => f <= w0 ; WHEN OTHERS => f <= w1 ; IF/ELS – in a PROCESS IF s = '0' THEN f <= w0 ; ELSE f <= w1 ; END IF ;

PROCESS Statement When there is a change in the value of any signal in the process’s sensitivity list, then the process becomes active. Once active, the statements inside the process are evaluated in sequential order. Any assignments made to signals inside the process are not visible outside the process until all of the statements in the process have been evaluated. If there are multiple assignments to the same signal, only the last one has any visible effect.